3d memory having vertical switches with surround gates and method thereof

ABSTRACT

A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.

CROSS-REFERENCE TO RELATED APPLICATIONS

The benefit is claimed for the following: United States provisionalpatent application of Raul Adrian Cernea and George Samachisa,Application No. 61/660,490 filed on Jun. 15, 2012; United Statesprovisional patent application of Raul Adrian Cernea, Application No.61/705,766 filed on Sep. 26, 2012; and United States provisional patentapplication of Yung-Tin Chen, Steve Radigan, Roy Scheuerlein, and RaulAdrian Cernea, Application No. 61/747,837 filed on Dec. 31, 2012.

BACKGROUND

The subject matter of this application is the structure, use and makingof re-programmable non-volatile memory cell arrays, and, morespecifically, to three-dimensional arrays of memory storage elementsformed on and above semiconductor substrates.

Uses of re-programmable non-volatile mass data storage systems utilizingflash memory are widespread for storing data of computer files, camerapictures, and data generated by and/or used by other types of hosts. Apopular form of flash memory is a card that is removably connected tothe host through a connector. There are many different flash memorycards that are commercially available, examples being those sold undertrademarks CompactFlash (CF), the MultiMediaCard (MMC), Secure Digital(SD), miniSD, microSD, Memory Stick, Memory Stick Micro, xD-PictureCard, SmartMedia and TransFlash. These cards have unique mechanicalplugs and/or electrical interfaces according to their specifications,and plug into mating receptacles provided as part of or connected withthe host.

Another form of flash memory systems in widespread use is the flashdrive, which is a hand held memory system in a small elongated packagethat has a Universal Serial Bus (USB) plug for connecting with a host byplugging it into the host's USB receptacle. SanDisk Corporation,assignee hereof, sells flash drives under its Cruzer, Ultra and ExtremeContour trademarks. In yet another form of flash memory systems, a largeamount of memory is permanently installed within host systems, such aswithin a notebook computer in place of the usual disk drive mass datastorage system. Each of these three forms of mass data storage systemsgenerally includes the same type of flash memory arrays. They each alsousually contain its own memory controller and drivers but there are alsosome memory only systems that are instead controlled at least in part bysoftware executed by the host to which the memory is connected. Theflash memory is typically formed on one or more integrated circuit chipsand the controller on another circuit chip. But in some memory systemsthat include the controller, especially those embedded within a host,the memory, controller and drivers are often formed on a singleintegrated circuit chip.

There are two primary techniques by which data are communicated betweenthe host and flash memory systems. In one of them, addresses of datafiles generated or received by the system are mapped into distinctranges of a continuous logical address space established for the system.The extent of the address space is typically sufficient to cover thefull range of addresses that the system is capable of handling. As oneexample, magnetic disk storage drives communicate with computers orother host systems through such a logical address space. The host systemkeeps track of the logical addresses assigned to its files by a fileallocation table (FAT) and the memory system maintains a map of thoselogical addresses into physical memory addresses where the data arestored. Most memory cards and flash drives that are commerciallyavailable utilize this type of interface since it emulates that ofmagnetic disk drives with which hosts have commonly interfaced.

In the second of the two techniques, data files generated by anelectronic system are uniquely identified and their data logicallyaddressed by offsets within the file. Theses file identifiers are thendirectly mapped within the memory system into physical memory locations.Both types of host/memory system interfaces are described and contrastedelsewhere, such as in patent application publication no. US 2006/0184720A1.

Flash memory systems typically utilize integrated circuits with arraysof memory cells that individually store an electrical charge thatcontrols the threshold level of the memory cells according to the databeing stored in them. Electrically conductive floating gates are mostcommonly provided as part of the memory cells to store the charge butdielectric charge trapping material is alternatively used. A NANDarchitecture is generally preferred for the memory cell arrays used forlarge capacity mass storage systems. Other architectures, such as NOR,are typically used instead for small capacity memories. Examples of NANDflash arrays and their operation as part of flash memory systems may behad by reference to U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935,6,373,746, 6,456,528, 6,522,580, 6,643,188, 6,771,536, 6,781,877 and7,342,279.

The amount of integrated circuit area necessary for each bit of datastored in the memory cell array has been reduced significantly over theyears, and the goal remains to reduce this further. The cost and size ofthe flash memory systems are therefore being reduced as a result. Theuse of the NAND array architecture contributes to this but otherapproaches have also been employed to reducing the size of memory cellarrays. One of these other approaches is to form, on a semiconductorsubstrate, multiple two-dimensional memory cell arrays, one on top ofanother in different planes, instead of the more typical single array.Examples of integrated circuits having multiple stacked NAND flashmemory cell array planes are given in U.S. Pat. Nos. 7,023,739 and7,177,191.

Another type of re-programmable non-volatile memory cell uses variableresistance memory elements that may be set to either conductive ornon-conductive states (or, alternately, low or high resistance states,respectively), and some additionally to partially conductive states andremain in that state until subsequently re-set to the initial condition.The variable resistance elements are individually connected between twoorthogonally extending conductors (typically bit and word lines) wherethey cross each other in a two-dimensional array. The state of such anelement is typically changed by proper voltages being placed on theintersecting conductors. Since these voltages are necessarily alsoapplied to a large number of other unselected resistive elements becausethey are connected along the same conductors as the states of selectedelements being programmed or read, diodes are commonly connected inseries with the variable resistive elements in order to reduce leakagecurrents that can flow through them. The desire to perform data readingand programming operations with a large number of memory cells inparallel results in reading or programming voltages being applied to avery large number of other memory cells. An example of an array ofvariable resistive memory elements and associated diodes is given inpatent application publication no. US 2009/0001344 A1.

SUMMARY OF THE INVENTION Vertical Switches With Surround Gates andMethod for Forming a Surround Gate of Vertical Switch in a 3D Memory

According to a general context of the invention, a nonvolatile memory isprovided with a 3D array of read/write (R/W) memory elements accessibleby an x-y-z framework of an array of local bit lines or bit line pillarsin the z-direction and word lines in multiple layers in the x-y planeperpendicular to the z-direction. An x-array of global bit lines in they-direction is switchably coupled to individual ones of the local bitline pillars along the y-direction. This is accomplished by a selecttransistor between each of the individual local bit line pillars and aglobal bit line. Each select transistor is a pillar select device thatis formed as a vertical structure, switching between a local bit linepillar and a global bit line.

According to another aspect of the invention, a 3D memory devicecomprises a vertical switching layer which serves to switch a set of oflocal bit lines to a corresponding set of global bit lines, the verticalswitching layer being a 2D array of TFT channels of vertical thin-filmtransistors (TFTs) aligned to connect to the array of local bit lines,each TFT switching a local bit line to a corresponding global bit lineand each TFT having a surround gate. In particular, the TFTs in thearray have a separation of lengths Lx and Ly along the x- and y-axisrespectively such that a gate material layer forms a surround gatearound each TFT in an x-y plane and has a thickness that merges to forma row select line along the x-axis while maintaining a separation oflength Ls between individual row select lines.

According to another aspect of the invention, in a 3D memory device withstructures arranged in a three-dimensional pattern defined byrectangular coordinates having x, y and z-directions and with aplurality of parallel x-y planes stacked in the vertical z-directionover a semiconductor substrate, and including a memory layer, a methodof forming a vertical switching layer which provides access to thememory layer comprises forming a 2-D array of TFT channels of verticalthin-film transistors (TFTs) to provide switching access to structuresin the memory layer, forming a gate oxide layer wrapping around each TFTchannel in the x-y plane, and forming a gate material layer over of thegate oxide layer, wherein the TFT channels in the 2-D array have aseparation of lengths Lx and Ly along the x- and y-axis respectively andsuch that said gate material layer has a thickness that merges to form arow select line along the x-axis while maintaining a separation oflength Ls between individual row select lines.

Generally, compared to CMOS transistors, thin-film transistors (TFTs) donot handle as much current. Having a surround gate effectively increasesthe channel area of the TFT and provide improved switching or drivingcapacity. The surrounding gate can deliver 3 times the drive currentcompared to a conventional single-side gate.

Various aspects, advantages, features and details of the innovativethree-dimensional variable resistive element memory system are includedin a description of exemplary examples thereof that follows, whichdescription should be taken in conjunction with the accompanyingdrawings.

All patents, patent applications, articles, other publications,documents and things referenced herein are hereby incorporated herein bythis reference in their entirety for all purposes. To the extent of anyinconsistency or conflict in the definition or use of terms between anyof the incorporated publications, documents or things and the presentapplication, those of the present application shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically an architecture of a three-dimensionalmemory in the form of an equivalent circuit of a portion of such amemory.

FIG. 2 is a block diagram of an illustrative memory system that can usethe three-dimensional memory of FIG. 1.

FIG. 3 provides plan views of the two planes and substrate of thethree-dimensional array of FIG. 1, with some structure added.

FIG. 4 is an expanded view of a portion of one of the planes of FIG. 3,annotated to show effects of programming data therein.

FIG. 5 is an expanded view of a portion of one of the planes of FIG. 3,annotated to show effects of reading data therefrom.

FIG. 6 illustrates an example memory storage element.

FIG. 7 illustrates the read bias voltages and current leakage acrossmultiple planes of the 3D memory shown in FIG. 1 and FIG. 3.

FIG. 8 illustrates schematically a single-sided word line architecture.

FIG. 9 illustrates one plane and substrate of the 3D array with thesingle-sided word line architecture.

FIG. 10 illustrates the elimination of leakage currents in thesingle-sided word-line architecture 3-D array of FIG. 8 and FIG. 9.

FIG. 11A illustrates the local bit line LBL₁₁ is coupled to the senseamplifier via a segment of global bit line GBL₁ having a length y1.

FIG. 11B illustrates the local bit line LBL₁₃ is coupled to the senseamplifier via a segment of global bit line GBL₁ having a length y2.

FIG. 12 illustrates the resistance along a circuit path of a selectedcell M between a word line driver and a sense amplifier.

FIG. 13 illustrates a bit line control circuit that keeps the bit linevoltage fixed to a reference voltage.

FIG. 14 is an isometric view of a portion of the 3D array with astructure having staircase word lines.

FIG. 15 illustrates a cross-section view of the 3D array along they-direction according to an embodiment in which the word line step tothe next memory layer is made in between the bit lines.

FIG. 16 illustrates a cross-section view of the 3D array along they-direction according to an embodiment in which the various staggeredword line steps are stacked as close as possible.

FIG. 17 illustrates from top to bottom a series of process steps tofabricate a 3D array with staircase word lines.

FIG. 18 illustrates a word line driver formed as a vertical structure ontop of the 3D array of memory layers.

FIG. 19A is a schematic illustration of a cross-section view of theefficient 3D array projected on the x-z plane.

FIG. 19B illustrates the device structure of the efficient 3D arrayshown schematically in FIG. 19A.

FIG. 20 is a schematic illustration of a cross-section view of theefficient 3D array projected on the x-z plane according to anotherembodiment.

FIG. 21 is an isometric view of a portion of the efficient 3D arrayshown in FIG. 19.

FIG. 22A illustrates one of a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where a masking layer islaid over the word line layer to enable trenches to be etched in theword line layer.

FIG. 22B illustrates one of a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where trenches are etchedin the word line layer.

FIG. 22C illustrates a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where an oxide layer isdeposited on top of the word line layer, followed by a masking layer.

FIG. 22D illustrates a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where trenches are etchedin the oxide layer.

FIG. 22E illustrates a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where a second word linelayer is formed on top of the oxide layer and making connection with thelower word line layer through the trenches in the oxide layer.

FIG. 22F illustrates a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where trenches are etchedin the second word line layer.

FIG. 22G illustrates a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where the process repeatsitself as in that shown in FIG. 22C for the next layer of oxide andmasking layer to build up the staircase structure of the word line.

FIG. 22H illustrates a series of process steps to fabricate theefficient 3D array shown in FIG. 19, including where the process repeatsitself as in that shown in FIG. 22D where trenches are etched in theoxide layer in order to build up progressively the staircase structureof the word line.

FIG. 23 illustrates the biasing condition for setting or resetting a R/Welement.

FIG. 24A is a perspective view illustrating an architecture for highcapacity local bit line switches.

FIG. 24B illustrates another embodiment of the high capacity local bitline switches.

FIG. 25 illustrates a cross sectional view of the switch shown in FIG.24A along the line z-z.

FIG. 26 illustrates the vertical select device in the overall scheme ofan exemplary 3D memory device in a cross-sectional view from they-direction along the global bit lines and perpendicular to the wordlines.

FIG. 27 is a schematic view in the x-y plane of a cross-section of thevertical switches in the select layer 2 for the 3D architecture shown inFIG. 21.

FIG. 28 illustrates the processes of forming of the vertical switchlayer 2, including depositing a layer of N+ poly on top of the memorylayer, followed by depositing a layer of P− poly and then a layer of N+poly.

FIG. 29A is a perspective view of the vertical switch layer 2 on top ofthe memory layer and illustrates the processes of forming the individualchannel pillars from the NPN slab.

FIG. 29B is a top plan view of FIG. 29A after the individual channelpillars have been formed.

FIG. 30A is a cross-sectional view along the x-axis illustratingdepositing a gate oxide layer on top of the channel pillars.

FIG. 30B is a cross-sectional view along the y-axis of FIG. 30A.

FIG. 31A is a cross-sectional view along the x-axis illustratingdepositing a gate material layer on top of the gate oxide layer.

FIG. 31B is a cross-sectional view along the y-axis of FIG. 31A showingthat the spacing between adjacent pair of insulated channel pillar arefilled with the gate material.

FIG. 32A is a cross-sectional view along the x-axis illustrating furtheretch back of the gate material layer.

FIG. 32B is a cross-sectional view along the y-axis of FIG. 32A.

FIG. 33A is a cross-sectional view along the x-axis illustrating theprocess of depositing oxide to fill in any pits and gaps to complete thevertical switch layer 2.

FIG. 33B is a cross-sectional view along the y-axis of FIG. 33A of thecompleted vertical switch layer 2 having an array of TFTs controlled byselect gate lines along the x-axis.

FIG. 34A is a cross-sectional view along the x-axis illustrating theprocess of forming global bit lines GBLs in the top metal layer.

FIG. 34B is a cross-sectional view along the y-axis of FIG. 34A.

FIG. 35 is a cross-sectional view along the x-axis illustrating theprocess of filling in the gaps between metal lines.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Referring initially to FIG. 1, an architecture of a three-dimensionalmemory 10 is schematically and generally illustrated in the form of anequivalent circuit of a portion of such a memory. This is a specificexample of the three-dimensional array summarized above. A standardthree-dimensional rectangular coordinate system 11 is used forreference, the directions of each of vectors x, y and z being orthogonalwith the other two.

A circuit for selectively connecting internal memory elements withexternal data circuits is preferably formed in a semiconductor substrate13. In this specific example, a two-dimensional array of select orswitching devices Q_(xy) are utilized, where x gives a relative positionof the device in the x-direction and y its relative position in they-direction. The individual devices Q_(xy) may be a select gate orselect transistor, as examples. Global bit lines (GBL_(x)) are elongatedin the y-direction and have relative positions in the x-direction thatare indicated by the subscript. The global bit lines (GBL_(x)) areindividually connectable with the source or drain of the select devicesQ having the same position in the x-direction, although during readingand also typically programming only one select device connected with aspecific global bit line is turned on at time. The other of the sourceor drain of the individual select devices Q is connected with one of thelocal bit lines (LBL_(xy)). The local bit lines are elongatedvertically, in the z-direction, and form a regular two-dimensional arrayin the x (row) and y (column) directions.

In order to connect one set (in this example, designated as one row) oflocal bit lines with corresponding global bit lines, control gate linesSG_(y) are elongated in the x-direction and connect with controlterminals (gates) of a single row of select devices Q_(xy) having acommon position in the y-direction. The select devices Q_(xy) thereforeconnect one row of local bit lines (LBL_(xy)) across the x-direction(having the same position in the y-direction) at a time to correspondingones of the global bit-lines (GBL_(x)), depending upon which of thecontrol gate lines SG_(y) receives a voltage that turns on the selectdevices to which it is connected. The remaining control gate linesreceive voltages that keep their connected select devices off. It may benoted that since only one select device (Q_(xy)) is used with each ofthe local bit lines (LBL_(xy)), the pitch of the array across thesemiconductor substrate in both x and y-directions may be made verysmall, and thus the density of the memory storage elements large.

Memory storage elements M_(zxy) are formed in a plurality of planespositioned at different distances in the z-direction above the substrate13. Two planes 1 and 2 are illustrated in FIG. 1 but there willtypically be more, such as 4, 6 or even more. In each plane at distancez, word lines WL_(zy) are elongated in the x-direction and spaced apartin the y-direction between the local bit-lines (LBL_(xy)). The wordlines WL of each plane individually cross adjacent two of the localbit-lines LBL_(xy) on either side of the word lines. The individualmemory storage elements M_(zxy) are connected between one local bit lineLBL_(xy) and one word line WL_(zy) adjacent these individual crossings.An individual memory element M_(zxy) is therefore addressable by placingproper voltages on the local bit line LBL_(xy) and word line WL_(zy)between which the memory element is connected. The voltages are chosento provide the electrical stimulus necessary to cause the state of thememory element to change from an existing state to the desired newstate. The levels, duration and other characteristics of these voltagesdepend upon the material that is used for the memory elements.

Each “plane” of the three-dimensional memory cell structure is typicallyformed of at least two layers, one in which the conductive word linesWL_(zy) are positioned and another of a dielectric material thatelectrically isolates the planes from each other. Additional layers mayalso be present in each plane, depending for example on the structure ofthe memory elements M_(zxy). The planes are stacked on top of each otheron a semiconductor substrate with the local bit lines LBL_(xy) beingconnected with storage elements M_(zxy) of each plane through which thelocal bit lines extend.

FIG. 2 is a block diagram of an illustrative memory system that can usethe three-dimensional memory 10 of FIG. 1. Sense amplifier and I/Ocircuits 21 are connected to provide (during programming) and receive(during reading) analog electrical quantities in parallel over theglobal bit-lines GBL_(x) of FIG. 1 that are representative of datastored in addressed storage elements M_(zxy). The circuits 21 typicallycontain sense amplifiers for converting these electrical quantities intodigital data values during reading, which digital values are thenconveyed over lines 23 to a memory system controller 25. Conversely,data to be programmed into the array 10 are sent by the controller 25 tothe sense amplifier and I/O circuits 21, which then programs that datainto addressed memory element by placing proper voltages on the globalbit lines GBL_(x). For binary operation, one voltage level is typicallyplaced on a global bit line to represent a binary “1” and anothervoltage level to represent a binary “0”. The memory elements areaddressed for reading or programming by voltages placed on the wordlines WL_(zy) and select gate control lines SG_(y) by respective wordline select circuits 27 and local bit line circuits 29. In the specificthree-dimensional array of FIG. 1, the memory elements lying between aselected word line and any of the local bit lines LBL_(xy) connected atone instance through the select devices Q_(xy) to the global bit linesGBL_(x) may be addressed for programming or reading by appropriatevoltages being applied through the select circuits 27 and 29.

The memory system controller 25 typically receives data from and sendsdata to a host system 31. The controller 25 usually contains an amountof random-access-memory (RAM) 34 for temporarily storing such data andoperating information. Commands, status signals and addresses of databeing read or programmed are also exchanged between the controller 25and host 31. The memory system operates with a wide variety of hostsystems. They include personal computers (PCs), laptop and otherportable computers, cellular telephones, personal digital assistants(PDAs), digital still cameras, digital movie cameras and portable audioplayers. The host typically includes a built-in receptacle 33 for one ormore types of memory cards or flash drives that accepts a mating memorysystem plug 35 of the memory system but some hosts require the use ofadapters into which a memory card is plugged, and others require the useof cables therebetween. Alternatively, the memory system may be builtinto the host system as an integral part thereof.

The memory system controller 25 conveys to decoder/driver circuits 37commands received from the host. Similarly, status signals generated bythe memory system are communicated to the controller 25 from thecircuits 37. The circuits 37 can be simple logic circuits in the casewhere the controller controls nearly all of the memory operations, orcan include a state machine to control at least some of the repetitivememory operations necessary to carry out given commands. Control signalsresulting from decoding commands are applied from the circuits 37 to theword line select circuits 27, local bit line select circuits 29 andsense amplifier and I/O circuits 21. Also connected to the circuits 27and 29 are address lines 39 from the controller that carry physicaladdresses of memory elements to be accessed within the array 10 in orderto carry out a command from the host. The physical addresses correspondto logical addresses received from the host system 31, the conversionbeing made by the controller 25 and/or the decoder/driver 37. As aresult, the circuits 29 partially address the designated storageelements within the array 10 by placing proper voltages on the controlelements of the select devices Q_(xy) to connect selected local bitlines (LBL_(xy)) with the global bit lines (GBL_(x)). The addressing iscompleted by the circuits 27 applying proper voltages to the word linesWL_(zy) of the array.

Although the memory system of FIG. 2 utilizes the three-dimensionalmemory element array 10 of FIG. 1, the system is not limited to use ofonly that array architecture. A given memory system may alternativelycombine this type of memory with other another type including flashmemory, such as flash having a NAND memory cell array architecture, amagnetic disk drive or some other type of memory. The other type ofmemory may have its own controller or may in some cases share thecontroller 25 with the three-dimensional memory cell array 10,particularly if there is some compatibility between the two types ofmemory at an operational level.

Although each of the memory elements M_(zxy) in the array of FIG. 1 maybe individually addressed for changing its state according to incomingdata or for reading its existing storage state, it is certainlypreferable to program and read the array in units of multiple memoryelements in parallel. In the three-dimensional array of FIG. 1, one rowof memory elements on one plane may be programmed and read in parallel.The number of memory elements operated in parallel depends on the numberof memory elements connected to the selected word line. In some arrays,the word lines may be segmented (not shown in FIG. 1) so that only aportion of the total number of memory elements connected along theirlength may be addressed for parallel operation, namely the memoryelements connected to a selected one of the segments.

Previously programmed memory elements whose data have become obsoletemay be addressed and re-programmed from the states in which they werepreviously programmed. The states of the memory elements beingre-programmed in parallel will therefore most often have differentstarting states among them. This is acceptable for many memory elementmaterials but it is usually preferred to re-set a group of memoryelements to a common state before they are re-programmed. For thispurpose, the memory elements may be grouped into blocks, where thememory elements of each block are simultaneously reset to a commonstate, preferably one of the programmed states, in preparation forsubsequently programming them. If the memory element material being usedis characterized by changing from a first to a second state insignificantly less time than it takes to be changed from the secondstate back to the first state, then the reset operation is preferablychosen to cause the transition taking the longer time to be made. Theprogramming is then done faster than resetting. The longer reset time isusually not a problem since resetting blocks of memory elementscontaining nothing but obsolete data is typically accomplished in a highpercentage of the cases in the background, therefore not adverselyimpacting the programming performance of the memory system.

With the use of block re-setting of memory elements, a three-dimensionalarray of variable resistive memory elements may be operated in a mannersimilar to current flash memory cell arrays. Resetting a block of memoryelements to a common state corresponds to erasing a block of flashmemory cells to an erased state. The individual blocks of memoryelements herein may be further divided into a plurality of pages ofstorage elements, wherein the memory elements of a page are programmedand read together. This is like the use of pages in flash memories. Thememory elements of an individual page are programmed and read together.Of course, when programming, those memory elements that are to storedata that are represented by the reset state are not changed from thereset state. Those of the memory elements of a page that need to bechanged to another state in order to represent the data being stored inthem have their states changed by the programming operation.

An example of use of such blocks and pages is illustrated in FIG. 3,which provides plan schematic views of planes 1 and 2 of the array ofFIG. 1. The different word lines WL_(zy) that extend across each of theplanes and the local bit lines LBL_(xy) that extend through the planesare shown in two-dimensions. Individual blocks are made up of memoryelements connected to both sides of one word line, or one segment of aword line if the word lines are segmented, in a single one of theplanes. There are therefore a very large number of such blocks in eachplane of the array. In the block illustrated in FIG. 3, each of thememory elements M₁₁₄, M₁₂₄, M₁₃₄, M₁₁₅, M₁₂₅ and M₁₃₅ connected to bothsides of one word line WL₁₂ form the block. Of course, there will bemany more memory elements connected along the length of a word line butonly a few of them are illustrated, for simplicity. The memory elementsof each block are connected between the single word line and differentones of the local bit lines, namely, for the block illustrated in FIG.3, between the word line WL₁₂ and respective local bit lines LBL₁₂,LBL₂₂, LBL₃₂, LBL₂₃ and LBL₃₃.

A page is also illustrated in FIG. 3. In the specific embodiment beingdescribed, there are two pages per block. One page is formed by thememory elements along one side of the word line of the block and theother page by the memory elements along the opposite side of the wordline. The example page marked in FIG. 3 is formed by memory elementsM₁₁₄, M₁₂₄ and M₁₃₄. Of course, a page will typically have a very largenumber of memory elements in order to be able to program and read alarge amount of data at one time. Only a few of the storage elements ofthe page of FIG. 3 are included, for simplicity in explanation.

Example resetting, programming and reading operations of the memoryarray of FIGS. 1 and 3, when operated as array 10 in the memory systemof FIG. 2, will now be described. For these examples, each of the memoryelements M_(zxy) is taken to include a non-volatile memory material thatcan be switched between two stable states of different resistance levelsby impressing voltages (or currents) of different polarity across thememory element, or voltages of the same polarity but differentmagnitudes and/or duration. For example, one class of material may beplaced into a high resistance state by passing current in one directionthrough the element, and into a low resistance state by passing currentin the other direction through the element. Or, in the case of switchingusing the same voltage polarity, one element may need a higher voltageand a shorter time to switch to a high resistance state and a lowervoltage and a longer time to switch to a lower resistance state. Theseare the two memory states of the individual memory elements thatindicate storage of one bit of data, which is either a “0” or a “1”,depending upon the memory element state.

To reset (erase) a block of memory elements, the memory elements in thatblock are placed into their high resistance state. This state will bedesignated as the logical data state “1”, following the convention usedin current flash memory arrays but it could alternatively be designatedto be a “0”. As shown by the example in FIG. 3, a block includes all thememory elements that are electrically connected to one word line WL orsegment thereof. A block is the smallest unit of memory elements in thearray that are reset together. It can include thousands of memoryelements. If a row of memory elements on one side of a word lineincludes 1000 of them, for example, a block will have 2000 memoryelements from the two rows on either side of the word line.

The following steps may be taken to reset all the memory elements of ablock, using the block illustrated in FIG. 3 as an example:

-   -   1. Set all of the global bit lines (GBL₁, GBL₂ and GBL₃ in the        array of FIGS. 1 and 3) to zero volts, by the sense amplifier        and I/O circuits 21 of FIG. 2.    -   2. Set at least the two select gate lines on either side of the        one word line of the block to H′ volts, so that the local bit        lines on each side of the word line in the y-direction are        connected to their respective global bit lines through their        select devices and therefore brought to zero volts. The voltage        H′ is made high enough to turn on the select devices Q_(xy),        like something in a range of 1-3 volts, typically 2 volts. The        block shown in FIG. 3 includes the word line WL₁₂, so the select        gate lines G₂ and SG₃ (FIG. 1) on either side of that word line        are set to H′ volts, by the circuits 29 of FIG. 2, in order to        turn on the select devices Q₁₂, Q₂₂, Q₃₂, Q₁₃, Q₂₃ and Q₃₃. This        causes each of the local bit lines LBL₁₂, LBL₂₂, LBL₃₂, LBL₁₃,        LBL₂₃ and LBL₃₃ in two adjacent rows extending in the        x-direction to be connected to respective ones of the global bit        lines GBL1, GBL2 and GBL3. Two of the local bit lines adjacent        to each other in the y-direction are connected to a single        global bit line. Those local bit lines are then set to the zero        volts of the global bit lines. The remaining local bit lines        preferably remain unconnected and with their voltages floating.    -   3. Set the word line of the block being reset to H volts. This        reset voltage value is dependent on the switching material in        the memory element and can be between a fraction of a volt to a        few volts. All other word lines of the array, including the        other word lines of selected plane 1 and all the word lines on        the other unselected planes, are set to zero volts. In the array        of FIGS. 1 and 3, word line WL₁₂ is placed at H volts, while all        other word lines in the array are placed at zero volts, all by        the circuits 27 of FIG. 2.

The result is that H volts are placed across each of the memory elementsof the block. In the example block of FIG. 3, this includes the memoryelements M₁₁₄, M₁₂₄, M₁₃₄, M₁₁₅, M₁₂₅ and M₁₃₅. For the type of memorymaterial being used as an example, the resulting currents through thesememory elements places any of them not already in a high resistancestate, into that re-set state.

It may be noted that no stray currents will flow because only one wordline has a non-zero voltage. The voltage on the one word line of theblock can cause current to flow to ground only through the memoryelements of the block. There is also nothing that can drive any of theunselected and electrically floating local bit lines to H volts, so novoltage difference will exist across any other memory elements of thearray outside of the block. Therefore no voltages are applied acrossunselected memory elements in other blocks that can cause them to beinadvertently disturbed or reset.

It may also be noted that multiple blocks may be concurrently reset bysetting any combination of word lines and the adjacent select gates to Hor H′ respectively. In this case, the only penalty for doing so is anincrease in the amount of current that is required to simultaneouslyreset an increased number of memory elements. This affects the size ofthe power supply that is required.

The memory elements of a page are preferably programmed concurrently, inorder to increase the parallelism of the memory system operation. Anexpanded version of the page indicated in FIG. 3 is provided in FIG. 4,with annotations added to illustrate a programming operation. Theindividual memory elements of the page are initially in their resetstate because all the memory elements of its block have previously beenreset. The reset state is taken herein to represent a logical data “1”.For any of these memory elements to store a logical data “0” inaccordance with incoming data being programmed into the page, thosememory elements are switched into their low resistance state, their setstate, while the remaining memory elements of the page remain in thereset state.

For programming a page, only one row of select devices is turned on,resulting in only one row of local bit lines being connected to theglobal bit lines. This connection alternatively allows the memoryelements of both pages of the block to be programmed in two sequentialprogramming cycles, which then makes the number of memory elements inthe reset and programming units equal.

Referring to FIGS. 3 and 4, an example programming operation within theindicated one page of memory elements M₁₁₄, M₁₂₄ and M₁₃₄ is described,as follows:

-   -   1. The voltages placed on the global bit lines are in accordance        with the pattern of data received by the memory system for        programming. In the example of FIG. 4, GBL₁ carries logical data        bit “1”, GBL₂ the logical bit “0” and GBL₃ the logical bit “1.”        The bit lines are set respectively to corresponding voltages M,        H and M, as shown, where the M level voltage is high but not        sufficient to program a memory element and the H level is high        enough to force a memory element into the programmed state. The        M level voltage may be about one-half of the H level voltage,        between zero volts and H. For example, a M level can be 0.7        volt, and a H level can be 1.5 volt. The H level used for        programming is not necessary the same as the H level used for        resetting or reading. In this case, according to the received        data, memory elements M₁₁₄ and M₁₃₄ are to remain in their reset        state, while memory element M₁₂₄ is being programmed. Therefore,        the programming voltages are applied only to memory element M₁₂₄        of this page by the following steps.    -   2. Set the word line of the page being programmed to 0 volts, in        this case selected word line WL₁₂. This is the only word line to        which the memory elements of the page are connected. Each of the        other word lines on all planes is set to the M level. These word        line voltages are applied by the circuits 27 of FIG. 2.    -   3. Set one of the select gate lines below and on either side of        the selected word line to the H′ voltage level, in order to        select a page for programming. For the page indicated in FIGS. 3        and 4, the H′ voltage is placed on select gate line SG₂ in order        to turn on select devices Q₁₂, Q₂₂ and Q₃₂ (FIG. 1). All other        select gate lines, namely lines SG₁ and SG₃ in this example, are        set to 0 volts in order to keep their select devices off. The        select gate line voltages are applied by the circuits 29 of        FIG. 2. This connects one row of local bit lines to the global        bit lines and leaves all other local bit lines floating. In this        example, the row of local bit lines LBL₁₂, LBL₂₂ and LBL₃₂ are        connected to the respective global bit lines GBL₁, GBL₂ and GBL₃        through the select devices that are turned on, while all other        local bit lines (LBLs) of the array are left floating.

The result of this operation, for the example memory element materialmentioned above, is that a programming current I_(PROG) is sent throughthe memory element M₁₂₄, thereby causing that memory element to changefrom a reset to a set (programmed) state. The same will occur with othermemory elements (not shown) that are connected between the selected wordline WL₁₂ and a local bit line (LBL) that has the programming voltagelevel H applied.

An example of the relative timing of applying the above-listedprogramming voltages is to initially set all the global bit lines(GBLs), the selected select gate line (SG), the selected word line andtwo adjacent word lines on either side of the selected word line on theone page all to the voltage level M. After this, selected ones of theGBLs are raised to the voltage level H according to the data beingprogrammed while simultaneously dropping the voltage of the selectedword line to 0 volts for the duration of the programming cycle. The wordlines in plane 1 other than the selected word line WL₁₂ and all wordlines in the unselected other planes can be weakly driven to M, somelower voltage or allowed to float in order to reduce power that must bedelivered by word line drivers that are part of the circuits 27 of FIG.2.

By floating all the local bit lines other than the selected row (in thisexample, all but LBL₁₂, LBL₂₂ and LBL₃₂), voltages can be looselycoupled to outer word lines of the selected plane 1 and word lines ofother planes that are allowed to float through memory elements in theirlow resistance state (programmed) that are connected between thefloating local bit lines and adjacent word lines. These outer word linesof the selected plane and word lines in unselected planes, althoughallowed to float, may eventually be driven up to voltage level M througha combination of programmed memory elements.

There are typically parasitic currents present during the programmingoperation that can increase the currents that must be supplied throughthe selected word line and global bit lines. During programming thereare two sources of parasitic currents, one to the adjacent page in adifferent block and another to the adjacent page in the same block. Anexample of the first is the parasitic current I_(P1) shown on FIG. 4from the local bit line LBL₂₂ that has been raised to the voltage levelH during programming. The memory element M₁₂₃ is connected between thatvoltage and the voltage level M on its word line WL₁₁. This voltagedifference can cause the parasitic current −I_(P1) to flow. Since thereis no such voltage difference between the local bit lines LBL₁₂ or LBL₃₂and the word line WL₁₁, no such parasitic current flows through eitherof the memory elements M₁₁₃ or M₁₃₃, a result of these memory elementsremaining in the reset state according to the data being programmed.

Other parasitic currents can similarly flow from the same local bit lineLBL₂₂ to an adjacent word line in other planes. The presence of thesecurrents may limit the number of planes that can be included in thememory system since the total current may increase with the number ofplanes. The limitation for programming is in the current capacity of thememory power supply, so the maximum number of planes is a tradeoffbetween the size of the power supply and the number of planes. A numberof 4-8 planes may generally be used in most cases.

The other source of parasitic currents during programming is to anadjacent page in the same block. The local bit lines that are leftfloating (all but those connected to the row of memory elements beingprogrammed) will tend to be driven to the voltage level M of unselectedword lines through any programmed memory element on any plane. This inturn can cause parasitic currents to flow in the selected plane fromthese local bit lines at the M voltage level to the selected word linethat is at zero volts. An example of this is given by the currentsI_(P2), I_(P3) and I_(P4) shown in FIG. 4. In general, these currentswill be much less than the other parasitic current I_(P1) discussedabove, since these currents flow only through those memory elements intheir conductive state that are adjacent to the selected word line inthe selected plane.

The above-described programming techniques ensure that the selected pageis programmed (local bit lines at H, selected word line at 0) and thatadjacent unselected word lines are at M. As mentioned earlier, otherunselected word lines can be weakly driven to M or initially driven to Mand then left floating. Alternately, word lines in any plane distantfrom the selected word line (for example, more than 5 word lines away)can also be left uncharged (at ground) or floating because the parasiticcurrents flowing to them are so low as to be negligible compared to theidentified parasitic currents since they must flow through a seriescombination of five or more ON devices (devices in their low resistancestate). This can reduce the power dissipation caused by charging a largenumber of word lines.

While the above description assumes that each memory element of the pagebeing programmed will reach its desired ON value with one application ofa programming pulse, a program-verify technique commonly used in NOR orNAND flash memory technology may alternately be used. In this process, acomplete programming operation for a given page includes of a series ofindividual programming operations in which a smaller change in ONresistance occurs within each program operation. Interspersed betweeneach program operation is a verify (read) operation that determineswhether an individual memory element has reached its desired programmedlevel of resistance or conductance consistent with the data beingprogrammed in the memory element. The sequence of program/verify isterminated for each memory element as it is verified to reach thedesired value of resistance or conductance. After all of memory elementsbeing programmed are verified to have reached their desired programmedvalue, programming of the page of memory elements is then completed. Anexample of this technique is described in U.S. Pat. No. 5,172,338.

With reference primarily to FIG. 5, the parallel reading of the statesof a page of memory elements, such as the memory elements M₁₁₄, M₁₂₄ andM₁₃₄, is described. The steps of an example reading process are asfollows:

-   -   1. Set all the global bit lines GBLs and all the word lines WL        to a voltage V_(R). The voltage V_(R) is simply a convenient        reference voltage and can be any number of values but will        typically be between 0 and 1 volt. In general, for operating        modes where repeated reads occur, it is convenient to set all        word lines in the array to V_(R) in order to reduce parasitic        read currents, even though this requires charging all the word        lines. However, as an alternative, it is only necessary to raise        the selected word line (WL₁₂ in FIG. 5), the word line in each        of the other planes that is in the same position as the selected        word line and the immediately adjacent word lines in all planes        to V_(R).    -   2. Turn on one row of select devices by placing a voltage on the        control line adjacent to the selected word line in order to        define the page to be read. In the example of FIGS. 1 and 5, a        voltage is applied to the control line SG₂ in order to turn on        the select devices Q₁₂, Q₂₂ and Q₃₂. This connects one row of        local bit lines LBL₁₂, LBL₂₂ and LBL₃₂ to their respective        global bit lines GBL₁, GBL₂ and GBL₃. These local bit lines are        then connected to individual sense amplifiers (SA) that are        present in the sense amplifier and I/O circuits 21 of FIG. 2,        and assume the potential V_(R) of the global bit lines to which        they are connected. All other local bit lines LBLs are allowed        to float.    -   3. Set the selected word line (WL₁₂) to a voltage of        V_(R)±Vsense. The sign of Vsense is chosen based on the sense        amplifier and has a magnitude of about 0.5 volt. The voltages on        all other word lines remain the same.    -   4. Sense current flowing into (V_(R)+Vsense) or out of        (V_(R)−Vsense) each sense amplifier for time T. These are the        currents I_(R1), I_(R2) and I_(R3) shown to be flowing through        the addressed memory elements of the example of FIG. 5, which        are proportional to the programmed states of the respective        memory elements M₁₁₄, M₁₂₄ and M₁₃₄. The states of the memory        elements M₁₁₄, M₁₂₄ and M₁₃₄ are then given by binary outputs of        the sense amplifiers within the sense amplifier and I/O circuits        21 that are connected to the respective global bit lines GBL₁,        GBL₂ and GBL₃. These sense amplifier outputs are then sent over        the lines 23 (FIG. 2) to the controller 25, which then provides        the read data to the host 31.    -   5. Turn off the select devices (Q₁₂, Q₂₂ and Q₃₂) by removing        the voltage from the select gate line (SG₂), in order to        disconnect the local bit lines from the global bit lines, and        return the selected word line (WL₁₂) to the voltage V_(R).

Parasitic currents during such a read operation have two undesirableeffects. As with programming, parasitic currents place increased demandson the memory system power supply. In addition, it is possible forparasitic currents to exist that are erroneously included in thecurrents though the addressed memory elements that are being read. Thiscan therefore lead to erroneous read results if such parasitic currentsare large enough.

As in the programming case, all of the local bit lines except theselected row (LBL₁₂, LBL₂₂ and LBL₃₂ in the example of FIG. 5) arefloating. But the potential of the floating local bit lines may bedriven to V_(R) by any memory element that is in its programmed (lowresistance) state and connected between a floating local bit line and aword line at V_(R), in any plane. A parasitic current comparable toI_(N) in the programming case (FIG. 4) is not present during data readbecause both the selected local bit lines and the adjacent non-selectedword lines are both at V_(R). Parasitic currents may flow, however,through low resistance memory elements connected between floating localbit lines and the selected word line. These are comparable to thecurrents I_(P2), I_(P3), and I_(P4) during programming (FIG. 4),indicated as I_(P5), I_(P6) and I_(P7) in FIG. 5. Each of these currentscan be equal in magnitude to the maximum read current through anaddressed memory element. However, these parasitic currents are flowingfrom the word lines at the voltage V_(R) to the selected word line at avoltage V_(R)±Vsense without flowing through the sense amplifiers. Theseparasitic currents will not flow through the selected local bit lines(LBL₁₂, LBL₂₂ and LBL₃₂ in FIG. 5) to which the sense amplifiers areconnected. Although they contribute to power dissipation, theseparasitic currents do not therefore introduce a sensing error.

Although the neighboring word lines should be at V_(R) to minimizeparasitic currents, as in the programming case it may be desirable toweakly drive these word lines or even allow them to float. In onevariation, the selected word line and the neighboring word lines can bepre-charged to V_(R) and then allowed to float. When the sense amplifieris energized, it may charge them to V_(R) so that the potential on theselines is accurately set by the reference voltage from the senseamplifier (as opposed to the reference voltage from the word linedriver). This can occur before the selected word line is changed toV_(R)±Vsense but the sense amplifier current is not measured until thischarging transient is completed.

Reference cells may also be included within the memory array 10 tofacilitate any or all of the common data operations (erase, program, orread). A reference cell is a cell that is structurally as nearlyidentical to a data cell as possible in which the resistance is set to aparticular value. They are useful to cancel or track resistance drift ofdata cells associated with temperature, process non-uniformities,repeated programming, time or other cell properties that may vary duringoperation of the memory. Typically they are set to have a resistanceabove the highest acceptable low resistance value of a memory element inone data state (such as the ON resistance) and below the lowestacceptable high resistance value of a memory element in another datastate (such as the OFF resistance). Reference cells may be “global” to aplane or the entire array, or may be contained within each block orpage.

In one embodiment, multiple reference cells may be contained within eachpage. The number of such cells may be only a few (less than 10), or maybe up to a several percent of the total number of cells within eachpage. In this case, the reference cells are typically reset and writtenin a separate operation independent of the data within the page. Forexample, they may be set one time in the factory, or they may be setonce or multiple times during operation of the memory array. During areset operation described above, all of the global bit lines are setlow, but this can be modified to only set the global bit linesassociated with the memory elements being reset to a low value while theglobal bit lines associated with the reference cells are set to anintermediate value, thus inhibiting them from being reset. Alternately,to reset reference cells within a given block, the global bit linesassociated with the reference cells are set to a low value while theglobal bit lines associated with the data cells are set to anintermediate value. During programming, this process is reversed and theglobal bit lines associated with the reference cells are raised to ahigh value to set the reference cells to a desired ON resistance whilethe memory elements remain in the reset state. Typically the programmingvoltages or times will be changed to program reference cells to a higherON resistance than when programming memory elements.

If, for example, the number of reference cells in each page is chosen tobe 1% of the number of data storage memory elements, then they may bephysically arranged along each word line such that each reference cellis separated from its neighbor by 100 data cells, and the senseamplifier associated with reading the reference cell can share itsreference information with the intervening sense amplifiers readingdata. Reference cells can be used during programming to ensure the datais programmed with sufficient margin. Further information regarding theuse of reference cells within a page can be found in U.S. Pat. Nos.6,222,762, 6,538,922, 6,678,192 and 7,237,074.

In a particular embodiment, reference cells may be used to approximatelycancel parasitic currents in the array. In this case the value of theresistance of the reference cell(s) is set to that of the reset staterather than a value between the reset state and a data state asdescribed earlier. The current in each reference cell can be measured byits associated sense amplifier and this current subtracted fromneighboring data cells. In this case, the reference cell isapproximating the parasitic currents flowing in a region of the memoryarray that tracks and is similar to the parasitic currents flowing inthat region of the array during a data operation. This correction can beapplied in a two-step operation (measure the parasitic current in thereference cells and subsequently subtract its value from that obtainedduring a data operation) or simultaneously with the data operation. Oneway in which simultaneous operation is possible is to use the referencecell to adjust the timing or reference levels of the adjacent data senseamplifiers. An example of this is shown in U.S. Pat. No. 7,324,393.

In conventional two-dimensional arrays of variable resistance memoryelements, a diode is usually included in series with the memory elementbetween the crossing bit and word lines. The primary purpose of thediodes is to reduce the number and magnitudes of parasitic currentsduring resetting (erasing), programming and reading the memory elements.A significant advantage of the three-dimensional array herein is thatresulting parasitic currents are fewer and therefore have a reducednegative effect on operation of the array than in other types of arrays.

Diodes may also be connected in series with the individual memoryelements of the three-dimensional array, as currently done in otherarrays of variable resistive memory elements, in order to reduce furtherthe number of parasitic currents but there are disadvantages in doingso. Primarily, the manufacturing process becomes more complicated. Addedmasks and added manufacturing steps are then necessary. Also, sinceformation of the silicon p-n diodes often requires at least one hightemperature step, the word lines and local bit lines cannot then be madeof metal having a low melting point, such as aluminum that is commonlyused in integrated circuit manufacturing, because it may melt during thesubsequent high temperature step. Use of a metal, or composite materialincluding a metal, is preferred because of its higher conductivity thanthe conductively doped polysilicon material that is typically used forbit and word lines because of being exposed to such high temperatures.An example of an array of resistive switching memory elements having adiode formed as part of the individual memory elements is given inpatent application publication no. US 2009/0001344 A1.

Because of the reduced number of parasitic currents in thethree-dimensional array herein, the total magnitude of parasiticcurrents can be managed without the use of such diodes. In addition tothe simpler manufacturing processes, the absence of the diodes allowsbi-polar operation; that is, an operation in which the voltage polarityto switch the memory element from its first state to its second memorystate is opposite of the voltage polarity to switch the memory elementfrom its second to its first memory state. The advantage of the bi-polaroperation over a unipolar operation (same polarity voltage is used toswitch the memory element from its first to second memory state as fromits second to first memory state) is the reduction of power to switchthe memory element and an improvement in the reliability of the memoryelement. These advantages of the bi-polar operation are seen in memoryelements in which formation and destruction of a conductive filament isthe physical mechanism for switching, as in the memory elements madefrom metal oxides and solid electrolyte materials.

The level of parasitic currents increases with the number of planes andwith the number of memory elements connected along the individual wordlines within each plane. But since the number of word lines on eachplane does not significantly affect the amount of parasitic current, theplanes may individually include a large number of word lines. Theparasitic currents resulting from a large number of memory elementsconnected along the length of individual word lines can further bemanaged by segmenting the word lines into sections of fewer numbers ofmemory elements. Erasing, programming and reading operations are thenperformed on the memory elements connected along one segment of eachword line instead of the total number of memory elements connected alongthe entire length of the word line.

The re-programmable non-volatile memory array being described herein hasmany advantages. The quantity of digital data that may be stored perunit of semiconductor substrate area is high. It may be manufacturedwith a lower cost per stored bit of data. Only a few masks are necessaryfor the entire stack of planes, rather than requiring a separate set ofmasks for each plane. The number of local bit line connections with thesubstrate is significantly reduced over other multi-plane structuresthat do not use the vertical local bit lines. The architectureeliminates the need for each memory cell to have a diode in series withthe resistive memory element, thereby further simplifying themanufacturing process and enabling the use of metal conductive lines.Also, the voltages necessary to operate the array are much lower thanthose used in current commercial flash memories.

Since at least one-half of each current path is vertical, the voltagedrops present in large cross-point arrays are significantly reduced. Thereduced length of the current path due to the shorter vertical componentmeans that there are approximately one-half the number memory cells oneach current path and thus the leakage currents are reduced as is thenumber of unselected cells disturbed during a data programming or readoperation. For example, if there are N cells associated with a word lineand N cells associated with a bit line of equal length in a conventionalarray, there are 2N cells associated or “touched” with every dataoperation. In the vertical local bit line architecture described herein,there are n cells associated with the bit line (n is the number ofplanes and is typically a small number such as 4 to 8), or N+n cells areassociated with a data operation. For a large N this means that thenumber of cells affected by a data operation is approximately one-halfas many as in a conventional three-dimensional array.

Materials Useful for the Memory Storage Elements

The material used for the non-volatile memory storage elements M_(zxy)in the array of FIG. 1 can be a chalcogenide, a metal oxide, or any oneof a number of materials that exhibit a stable, reversible shift inresistance in response to an external voltage applied to or currentpassed through the material.

Metal oxides are characterized by being insulating when initiallydeposited. One suitable metal oxide is a titanium oxide (TiO_(x)). Apreviously reported memory element using this material is illustrated inFIG. 6. In this case, near-stoichiometric TiO₂ bulk material is alteredin an annealing process to create an oxygen deficient layer (or a layerwith oxygen vacancies) in proximity of the bottom electrode. The topplatinum electrode, with its high work function, creates a highpotential Pt/TiO₂ barrier for electrons. As a result, at moderatevoltages (below one volt), a very low current will flow through thestructure. The bottom Pt/TiO_(2x) barrier is lowered by the presence ofthe oxygen vacancies (O⁺ ₂) and behaves as a low resistance contact(ohmic contact). (The oxygen vacancies in TiO₂ are known to act asn-type dopant, transforming the insulating oxide in an electricallyconductive doped semiconductor.) The resulting composite structure is ina non-conductive (high resistance) state.

But when a large negative voltage (such as 1.5 volt) is applied acrossthe structure, the oxygen vacancies drift toward the top electrode and,as a result, the potential barrier Pt/TiO₂ is reduced and a relativelyhigh current can flow through the structure. The device is then in itslow resistance (conductive) state. Experiments reported by others haveshown that conduction is occurring in filament-like regions of the TiO₂,perhaps along grain boundaries.

The conductive path is broken by applying a large positive voltageacross the structure of FIG. 6. Under this positive bias, the oxygenvacancies move away from the proximity of the top Pt/TiO₂ barrier, and“break” the filament. The device returns to its high resistance state.Both of the conductive and non-conductive states are non-volatile.Sensing the conduction of the memory storage element by applying avoltage around 0.5 volts can easily determine the state of the memoryelement.

While this specific conduction mechanism may not apply to all metaloxides, as a group, they have a similar behavior: transition from a lowconductive state to a high conductive occurs state when appropriatevoltages are applied, and the two states are non-volatile. Examples ofother materials include HfOx, ZrOx, WOx, NiOx, CoOx, CoalOx, MnOx,ZnMn₂O₄, ZnOx, TaOx, NbOx, HfSiOx, HfAlOx. Suitable top electrodesinclude metals with a high work function (typically >4.5 eV) capable togetter oxygen in contact with the metal oxide to create oxygen vacanciesat the contact. Some examples are TaCN, TiCN, Ru, RuO, Pt, Ti rich TiOx,TiAlN, TaAlN, TiSiN, TaSiN, IrO₂. Suitable materials for the bottomelectrode are any conducting oxygen rich material such as Ti(O)N,Ta(O)N, TiN and TaN. The thicknesses of the electrodes are typically 1nm or greater. Thicknesses of the metal oxide are generally in the rangeof 5 nm to 50 nm.

Another class of materials suitable for the memory storage elements issolid electrolytes but since they are electrically conductive whendeposited, individual memory elements need to be formed and isolatedfrom one another. Solid electrolytes are somewhat similar to the metaloxides, and the conduction mechanism is assumed to be the formation of ametallic filament between the top and bottom electrode. In thisstructure the filament is formed by dissolving ions from one electrode(the oxidizable electrode) into the body of the cell (the solidelectrolyte). In one example, the solid electrolyte contains silver ionsor copper ions, and the oxidizable electrode is preferably a metalintercalated in a transition metal sulfide or selenide material such asA_(x)(MB2)_(1-x), where A is Ag or Cu, B is S or Se, and M is atransition metal such as Ta, V, or Ti, and x ranges from about 0.1 toabout 0.7. Such a composition minimizes oxidizing unwanted material intothe solid electrolyte. One example of such a composition isAg_(x)(TaS2)_(1-x). Alternate composition materials include α-AgI. Theother electrode (the indifferent or neutral electrode) should be a goodelectrical conductor while remaining insoluble in the solid electrolytematerial. Examples include metals and compounds such as W, Ni, Mo, Pt,metal silicides, and the like.

Examples of solid electrolytes materials are: TaO, GeSe or GeS. Othersystems suitable for use as solid electrolyte cells are: Cu/TaO/W,Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W, and Ag/GeS/W, where the first materialis the oxidizable electrode, the middle material is the solidelectrolyte, and the third material is the indifferent (neutral)electrode. Typical thicknesses of the solid electrolyte are between 30nm and 100 nm.

In recent years, carbon has been extensively studied as a non-volatilememory material. As a non-volatile memory element, carbon is usuallyused in two forms, conductive (or grapheme like-carbon) and insulating(or amorphous carbon). The difference in the two types of carbonmaterial is the content of the carbon chemical bonds, so called sp² andsp³ hybridizations. In the sp³ configuration, the carbon valenceelectrons are kept in strong covalent bonds and as a result the sp³hybridization is non-conductive. Carbon films in which the sp³configuration dominates, are commonly referred to astetrahedral-amorphous carbon, or diamond like. In the sp² configuration,not all the carbon valence electrons are kept in covalent bonds. Theweak tight electrons (phi bonds) contribute to the electrical conductionmaking the mostly sp² configuration a conductive carbon material. Theoperation of the carbon resistive switching nonvolatile memories isbased on the fact that it is possible to transform the sp³ configurationto the sp² configuration by applying appropriate current (or voltage)pulses to the carbon structure. For example, when a very short (1-5 ns)high amplitude voltage pulse is applied across the material, theconductance is greatly reduced as the material sp² changes into an sp³form (“reset” state). It has been theorized that the high localtemperatures generated by this pulse causes disorder in the material andif the pulse is very short, the carbon “quenches” in an amorphous state(sp³ hybridization). On the other hand, when in the reset state,applying a lower voltage for a longer time (˜300 nsec) causes part ofthe material to change into the sp² form (“set” state). The carbonresistance switching non-volatile memory elements have a capacitor likeconfiguration where the top and bottom electrodes are made of hightemperature melting point metals like W, Pd, Pt and TaN.

There has been significant attention recently to the application ofcarbon nanotubes (CNTs) as a non-volatile memory material. A (singlewalled) carbon nanotube is a hollow cylinder of carbon, typically arolled and self-closing sheet one carbon atom thick, with a typicaldiameter of about 1-2 nm and a length hundreds of times greater. Suchnanotubes can demonstrate very high conductivity, and various proposalshave been made regarding compatibility with integrated circuitfabrication. It has been proposed to encapsulate “short” CNT's within aninert binder matrix to form a fabric of CNT's. These can be deposited ona silicon wafer using a spin-on or spray coating, and as applied theCNT's have a random orientation with respect to each other. When anelectric field is applied across this fabric, the CNT's tend to flex oralign themselves such that the conductivity of the fabric is changed.The switching mechanism from low-to-high resistance and the opposite isnot well understood. As in the other carbon based resistive switchingnon-volatile memories, the CNT based memories have capacitor-likeconfigurations with top and bottom electrodes made of high melting pointmetals such as those mentioned above.

Yet another class of materials suitable for the memory storage elementsis phase-change materials. A preferred group of phase-change materialsincludes chalcogenide glasses, often of a compositionGe_(x)Sb_(y)Te_(z), where preferably x=2, y=2 and z=5. GeSb has alsobeen found to be useful. Other materials include AgInSbTe, GeTe, GaSb,BaSbTe, InSbTe and various other combinations of these basic elements.Thicknesses are generally in the range of 1 nm to 500 nm. The generallyaccepted explanation for the switching mechanism is that when a highenergy pulse is applied for a very short time to cause a region of thematerial to melt, the material “quenches” in an amorphous state, whichis a low conductive state. When a lower energy pulse is applied for alonger time such that the temperature remains above the crystallizationtemperature but below the melting temperature, the material crystallizesto form poly-crystal phases of high conductivity. These devices areoften fabricated using sub-lithographic pillars, integrated with heaterelectrodes. Often the localized region undergoing the phase change maybe designed to correspond to a transition over a step edge, or a regionwhere the material crosses over a slot etched in a low thermalconductivity material. The contacting electrodes may be any high meltingmetal such as TiN, W, WN and TaN in thicknesses from 1 nm to 500 nm.

It will be noted that the memory materials in most of the foregoingexamples utilize electrodes on either side thereof whose compositionsare specifically selected. In embodiments of the three-dimensionalmemory array herein where the word lines (WL) and/or local bit lines(LBL) also form these electrodes by direct contact with the memorymaterial, those lines are preferably made of the conductive materialsdescribed above. In embodiments using additional conductive segments forat least one of the two memory element electrodes, those segments aretherefore made of the materials described above for the memory elementelectrodes.

Steering elements are commonly incorporated into controllable resistancetypes of memory storage elements. Steering elements can be a transistoror a diode. Although an advantage of the three-dimensional architecturedescribed herein is that such steering elements are not necessary, theremay be specific configurations where it is desirable to include steeringelements. The diode can be a p-n junction (not necessarily of silicon),a metal/insulator/insulator/metal (MIIM), or a Schottky typemetal/semiconductor contact but can alternately be a solid electrolyteelement. A characteristic of this type of diode is that for correctoperation in a memory array, it is necessary to be switched “on” and“off” during each address operation. Until the memory element isaddressed, the diode is in the high resistance state (”off” state) and“shields” the resistive memory element from disturb voltages. To accessa resistive memory element, three different operations are needed: a)convert the diode from high resistance to low resistance, b) program,read, or reset (erase) the memory element by application of appropriatevoltages across or currents through the diode, and c) reset (erase) thediode. In some embodiments one or more of these operations can becombined into the same step. Resetting the diode may be accomplished byapplying a reverse voltage to the memory element including a diode,which causes the diode filament to collapse and the diode to return tothe high resistance state.

For simplicity the above description has consider the simplest case ofstoring one data value within each cell: each cell is either reset orset and holds one bit of data. However, the techniques of the presentapplication are not limited to this simple case. By using various valuesof ON resistance and designing the sense amplifiers to be able todiscriminate between several of such values, each memory element canhold multiple-bits of data in a multiple-level cell (MLC). Theprinciples of such operation are described in U.S. Pat. No. 5,172,338referenced earlier. Examples of MLC technology applied to threedimensional arrays of memory elements include an article entitled“Multi-bit Memory Using Programmable Metallization Cell Technology” byKozicki et al., Proceedings of the International Conference onElectronic Devices and Memory, Grenoble, France, Jun. 12-17, 2005, pp.48-53 and “Time Discrete Voltage Sensing and Iterative ProgrammingControl for a 4F2 Multilevel CBRAM” by Schrogmeier et al. (2007Symposium on VLSI Circuits).

Conventionally, diodes are commonly connected in series with thevariable resistive elements of a memory array in order to reduce leakagecurrents that can flow through them. The highly compact 3Dreprogrammable memory described in the present invention has anarchitecture that does not require a diode in series with each memoryelement while able to keep the leakage currents reduced. (Of course,using a diode will further control the leakage currents at the expenseof more processing and possible more occupied space.) This is possiblewith short local vertical bit lines which are selectively coupled to aset of global bit lines. In this manner, the structures of the 3D memoryare necessarily segmented and couplings between the individual paths inthe mesh are reduced.

Even if the 3D reprogrammable memory has an architecture that allowsreduced current leakage, it is desirable to further reduce them. Asdescribed earlier and in connection with FIG. 5, parasitic currents mayexist during a read operation and these currents have two undesirableeffects. First, they result in higher power consumption. Secondly, andmore seriously, they may occur in the sensing path of the memory elementbeing sensed, cause erroneous reading of the sensed current.

FIG. 7 illustrates the read bias voltages and current leakage acrossmultiple planes of the 3D memory shown in FIG. 1 and FIG. 3. FIG. 7 is across-sectional view across 4 planes along the x-direction of a portionof the perspective 3D view of the memory shown in FIG. 1. It should beclear that while FIG. 1 shows the substrate and 2 planes, FIG. 7 showsthe substrate and 4 planes to better illustrate the effect of currentleakage from one plane to another.

In accordance with the general principle described in connection withFIG. 5, when the resistive state of a memory element 200 in FIG. 7 is tobe determined, a bias voltage is applied across the memory element andits element current I_(ELEMENT) sensed. The memory element 200 resideson Plane 4 and is accessible by selecting the word line 210 (Sel-WLi)and the local bit line 220 (Sel-LBLj). For example, to apply the biasvoltage, the selected word line 210 (Sel-WLi) is set to 0 v and thecorresponding selected local bit line 220 (Sel-LBLj) is set to areference such as 0.5V via a turned on select gate 222 by a senseamplifier 240. With all other unselected word line in all planes alsoset to the reference 0.5V and all unselected local bit lines also set tothe reference 0.5V, then the current sensed by the sense amplifier 240will just be the I_(ELEMENT) of the memory element 200.

The architecture shown in FIG. 1 and FIG. 7 has the unselected local bitlines (LBLj+1, LBLj+2, . . . ) and the selected local bit line(Sel-LBLj) all sharing the same global bit line 250 (GBLi) to the senseamplifier 240. During sensing of the memory element 200, the unselectedlocal bit lines can only be isolated from the sense amplifier 240 byhaving their respective select gate such as gate 232 turned off. In thisway, the unselected local bit lines are left floating and will couple tothe reference 0.5V by virtue of adjacent nodes which are at 0.5V.However, the adjacent nodes are not exactly at the reference 0.5V. Thisis due to a finite resistance in each word line (perpendicular to theplane in FIG. 7) which results in a progressive voltage drop away fromone end of the word line at which 0.5V is applied. This ultimatelyresults in the floating, adjacent unselected local bit lines coupling toa voltage slightly different from the reference 0.5V. In this instance,there will be leakage currents between the selected and unselected localbit lines as illustrated by broken flow lines in FIG. 7. Then sensedcurrent is then I_(ELEMENT)+leakage currents instead of justI_(ELEMENT). This problem becomes worse will increasing word line'slength and resistivity.

Another 3D memory architecture includes memory elements arranged in athree-dimensional pattern defined by rectangular coordinates having x, yand z-directions and with a plurality of parallel planes stacked in thez-direction. The memory elements in each plane are accessed by aplurality of word lines and local bit lines in tandem with a pluralityof global bit lines. The plurality of local bit lines are in thez-direction through the plurality of planes and arranged in a twodimensional rectangular array of rows in the x-direction and columns inthe y-directions. The plurality of word lines in each plane areelongated in the x-direction and spaced apart in the y-direction betweenand separated from the plurality of local bit lines in the individualplanes. A non-volatile, reprogramming memory element is located near acrossing between a word line and local bit line and accessible by theword line and bit line and wherein a group of memory elements areaccessible in parallel by a common word line and a row of local bitlines. The 3D memory has a single-sided word line architecture with eachword line exclusively connected to one row of memory elements. This isaccomplished by providing one word line for each row of memory elementsinstead of sharing one word line between two rows of memory elements andlinking the memory element across the array across the word lines. Whilethe row of memory elements is also being accessed by a corresponding rowof local bit lines, there is no extension of coupling for the row oflocal bit lines beyond the word line.

A double-sided word line architecture has been described earlier in thateach word line is connected to two adjacent rows of memory elementsassociated with two corresponding rows of local bit lines, one adjacentrow along one side of the word line and another adjacent row along theother side. For example, as shown in FIG. 1 and FIG. 3, the word lineWL₁₂ is connected on one side to a first row (or page) of memoryelements (M₁₁₄, M₁₂₄, M₁₃₄, . . . ) associated respectively with localbit lines (LBL₁₂, LBL₂₂, LBL₃₂, . . . ) and also connected on anotherside to a second row (or page) of memory elements (M₁₁₅, M₁₂₅, M₁₃₅, . .. ) associated respectively with local bit lines (LBL₁₃, LBL₂₃, LBL₃₃, .. . )

FIG. 8 illustrates schematically a single-sided word line architecture.Each word line is connected to an adjacent row of memory elementsassociate with one row of local bit lines on only one side.

The 3D memory array with the double-sided word line architectureillustrated in FIG. 1 can be modified to the single-sided word linearchitecture where each word line except ones at an edge of the arraywill be replaced by a pair of word lines. In this way, each word line isconnecting exclusively to one row of memory elements. Thus, the wordline WL₁₂ shown in FIG. 1 is now replaced in FIG. 8 by the pair of wordlines WL₁₃ and WL₁₄. It will be seen that WL13 is connected to one rowof memory elements (M₁₁₄, M₁₂₄, M₁₃₄, . . . ) and WL14 is connected toone row of memory elements (M₁₁₅, M₁₂₅, M₁₃₅, . . . ) As describedbefore, a row of memory elements constitutes a page which is read orwritten to in parallel.

FIG. 9 illustrates one plane and substrate of the 3D array with thesingle-sided word line architecture. Going from the double-sided wordline architecture of FIG. 3, similarly, WL₁₂ in FIG. 3 would be replacedby the pair WL₁₃, WL₁₄ in FIG. 9, etc. In FIG. 3, a typical double-sidedword line (e.g., WL₁₂) is connected to two rows of memory elements (onboth side of the word line). In FIG. 9, each single-sided word line(e.g., WL₁₃) is connected to only one row of memory elements.

FIG. 9 also illustrates a minimum block of memory elements that iserasable as a unit to be defined by two row of memory elements (M₁₁₃,M₁₂₃, M₁₃₃, . . . ) and (M₁₁₄, M₁₂₄, M₁₃₄, . . . ) sharing the same rowof local bit lines (e.g., LBL₁₂, LBL₂₂, LBL₃₂, . . . )

FIG. 10 illustrates the elimination of leakage currents in thesingle-sided word-line architecture 3-D array of FIGS. 8 and 9. Theanalysis of leakage current is similar to that described with respect toFIG. 7. However, with the single-sided word-line architecture, theselected local bit line 220 (Sel-LBLj) is not coupled to an adjacent bitline 230 across the separated word lines 210 and 212. Thus there is noleakage current between adjacent local bit lines and the sense currentin the sense amplifier 240 via the global bit line 250 and the local bitline 220 will be just that from the current of the memory elementI_(ELEMENT).

The single-sided word-line architecture doubles the number of word linesin the memory array compared to the architecture shown in FIG. 1.However, this disadvantage is offset by providing a memory array withless leakage currents among the memory elements.

The single-sided word-line architecture is disclosed in PCTInternational Publication No. WO 2010/117914 A1, and United StatesPatent Application Publication No. 20120147650, the entire disclosure ofthese are incorporated herein by reference.

Sensing Error Due to Local Bit Line Voltage Variations

As described in the embodiments of FIG. 1 and FIG. 8, a selected R/Welement, M, is accessed by a pair of selected word line WL and local bitline LBL. The local bit line LBL is one among a 2D array of bit linepillars. Each bit line pillar LBL is switchably connected by a bit linepillar switch to a node on a corresponding global bit line GBL. In aread operation, the current through the R/W element is sensed by a senseamplifier via the global bit line GBL coupled to the selected local bitline LBL. The examples given in FIG. 7 and FIG. 10 has the R/W element,M, connected between a selected local bit line and a selected word line.The selected local bit line is set to 0.5V and the selected word line isset to 0V. The voltages on the word lines are driven by a set of wordline drivers. All other word lines and local bit lines are preferableset to the same voltage as the selected local bit line to eliminatecurrent leakage.

The voltage on a local bit line is sourced from a bit line driverassociated with a sense amplifier, typically located on one end of aglobal bit line. The voltage established on a local bit line could behighly variable dependent on the position of a connection node the localbit line makes along the global bit line as well as the resistive stateof the cell (R/W element) it is accessing.

The voltages of the individual local bit line are dependent on thepositions of the respective local bit lines or connection nodes on theglobal bit line relative to the bit line driver. A local bit line LBL isrelative short, as it only transverses the layers across thez-direction, so the voltage drop along it is insignificant. However, theglobal bit line is long in comparison, and due to the finite resistanceof the global bit line, an IR voltage drop along it can cause the bitline driver to supply reduced voltage to the local bit line.Furthermore, the reduced voltage is dependent on the position of theconnection node the local bit line makes with the global bit line.

FIGS. 11A and 11B respectively illustrate the different path lengths oftwo local bit lines to their sense amplifiers. A voltage VDD is suppliedto the global bit line GBL₁ via the sense amplifier 240. In FIG. 11A,the local bit line LBL₁₁ 260-11 is coupled to the sense amplifier 240via a segment 270-y 1 of global bit line GBL₁ having a length y1 . Thusthe IR drop in the path due to the segment 270-y 1 is IR_(GBL(y1)). InFIG. 11B, the local bit line LBL₁₃ 260-13 is coupled to the senseamplifier 240 via a segment 270-y 2 of global bit line GBL₁ having alength y2. Thus the IR drop in the path due to the segment 270-y 2 isIR_(GBL(y2)).

The problem is further exacerbated if the bit line driver is sensitiveto the serial resistance of the circuit path during sensing, as is thecase with a source-follower configuration. The bit line voltage in thiscase depends upon the current flowing through the transistor of thesource follower. Thus, the various bit lines could be driven todifferent voltages depending on the serial resistance in the respectivecircuit paths.

FIG. 12 illustrates the resistance along a circuit path of a selectedcell M between a word line driver and a sense amplifier. The senseamplifier also acts as a bit line driver. The resistance includes theresistance of a segment of the selected word line (R_(WL(x))), theresistance of the R/W element (R_(M)) which is state dependent, theresistance of the segment of the global bit line (R_(GBL(y))) and theresistance of the sense amplifier (R_(SA)).

The cell's actual current value and cell's current reading by the senseamplifier are both affected by cell position, sense amplifierresistance, data pattern of neighboring cells and word line resistivity.In an ideal situation, if a cell is close to the sense amplifier,R_(GBL(y=)0)=0. If the sense amplifier is emulated by VDD, R_(SA)=0. Ifthe word line is ideally conductive, R_(WL(x))=0.

In general, these resistances all contribute to reducing the cellcurrent. With the cell farther away from the bit line driver and a realsense amplifier, and more conductive neighboring cells, alternativepaths become more and more significant. Thus, the sense amplifier willread a cell current reduced from its actual one.

The non-constant voltages among the local bit lines will exacerbatecurrent leakage in the network of the 3D array. For example, theadjacent unselected word lines are biased to the same voltage as theselected local bit line to avoid leakage and it will be uncertain if thelocal bit line voltage is variable.

Worst still during read, the non-uniform local bit line voltage willlead to loss of margin between the different resistive states of the R/Welements and cause memory states to be the overlapping andindistinguishable.

Bit Line Voltage Control

According to one aspect of the invention, each local bit line isswitchably connected to a node on a global bit line having first andsecond ends, and the voltage on the local bit line is maintained at apredetermined reference level in spite of being driven by a bit linedriver from a first end of the global bit line that constitutes variablecircuit path length and circuit serial resistance. This is accomplishedby a feedback voltage regulator comprising a voltage clamp at the firstend of the global bit line controlled by a bit line voltage comparatorat the second end of the global bit line. The bit line voltage is sensedaccurately from the second end of the global bit line since there is nocurrent flow to incur an IR drop. The comparator compares the sensed bitline voltage with the predetermined reference level and outputs acontrol voltage. The voltage clamp is controlled by the control voltageas part of the feedback circuit. In this way the voltage at the localbit line is regulated at the reference voltage.

FIG. 13 illustrates a bit line control circuit that keeps the bit linevoltage fixed relative to a reference voltage. A sense amplifier 240 isconnected to a first end 271 of the global bit line GBL 270. The localbit line LBL 260 is coupled to the sense amplifier via a first segment270-1 of the GBL 270. The sense amplifier serves as a bit line driver todrive the local bit line LBL 260 to a given voltage as well as sensing acurrent in the local bit line. The remaining portion of the GBL formsthe second segment 270-2 of the GBL 270. A voltage clamp (BL Clamp) 280operates with a supply voltage from the sense amplifier to clamp thevoltage at the LBL 260. The actual voltage V_(LBL) at the LBL 260 can bedetected from a second end 273 of the GBL 270 via the second segment270-2. Since no current flows in the second segment 270-2, there is noIR drop in the second segment. This actual voltage is compared to apredetermined reference voltage 286 by a comparator 284 such as an opamp. The output of the comparator 282 feeds a control voltage Vc tocontrol the BL clamp 280. For example, the BL clamp 280 can beimplemented by a transistor, with the output of the comparator Vcsupplied to the gate 282 of the transistor. In order to maintain apredetermined local bit line voltage of V_(LBL), the predeterminedreference voltage is set to V_(LBL) in order to have the comparator 284outputs a feedback control voltage Vc=V_(LBL)+V_(T)+ΔV where V_(T) isthe threshold of the transistor and ΔV is the feedback adjustment. Inthis way, the voltage of the local bit line 260 can be set to apredetermined value irrespective of the variable resistance R_(GBL(y))of the first segment 270-1 of the global bit line GBL 270 to the voltagesupply (via the sense amplifier).

One implementation of the bit line voltage control circuit is to havethe sense amplifiers 240 located at the first end 271 of the global bitline 270 in the 3D array and the comparator 282 located at the secondend 273 of the global bit line. A conducting line 283 connects theoutput of the comparator 284 to the voltage clamp 280 across and underthe 3D array. The bit line voltage control circuit can be implemented asanother layer below the 3D array.

When the voltages of the local bit lines in the 3D array are wellcontrolled during read and programming, the problems of leakage and lossof margin mentioned above are reduced.

3D Array Architecture with Staircase Word Lines

According to one aspect of the invention, a nonvolatile memory isprovided with a 3D array of read/write (R/W) memory elements accessibleby an x-y-z framework of an array of local bit lines or bit line pillarsin the z-direction and word lines in multiple memory planes or layers inthe x-y plane perpendicular to the z-direction. An x-array of global bitlines in the y-direction is switchably coupled to individual ones of thelocal bit line pillars along the y-direction.

Furthermore, the switchably coupling of a local bit line pillar to acorresponding global bit line is accomplished by a select transistor.The select transistor is a pillar select device that is formed as avertical structure, switching between a local bit line pillar and aglobal bit line. The pillar select devices, are not formed within a CMOSlayer, but are formed in a separate layer (pillar select layer) abovethe CMOS layer, along the z-direction between the array of global bitlines and the array of local bit lines.

Furthermore, each word line has multiple segments in a staircasestructure traversing the multiple memory layers in which each segment ofthe staircase word line lies in a memory plane or layer. Thus each wordline has a segment in each memory layer and ultimately rises to the topof the 3D array as an exposed word line segment to be connected to aword line driver.

In a 3D nonvolatile memory with memory elements arranged in athree-dimensional pattern defined by rectangular coordinates having x, yand z-directions and with a plurality of parallel planes from a bottomplane to a top plane stacked in the z-direction over a semiconductorsubstrate; a plurality of local bit lines elongated in the z-directionthrough the plurality of layers and arranged in a two-dimensionalrectangular array of bit line pillars having rows in the x-direction andcolumns in the y-direction; the 3D nonvolatile memory further having aplurality of staircase word lines spaced apart in the y-direction andbetween and separated from the plurality of bit line pillars at aplurality of crossings, individual staircase word lines each having aseries of alternating steps and risers elongated respectively in thex-direction and z-direction traversing across the plurality of planes inthe z-direction with a segment in each plane.

FIG. 14 is an isometric view of a portion of the 3D array 300 with astructure having staircase word lines 310. The gross structure is a 3Darray of memory cells M at crossings between a 2D array of local bitlines LBLs in the z-direction and segments of word lines WLs in eachmemory layer in the x-y plane.

In this embodiment, the local bit lines LBL 320 are in the form of bitline pillars LBLs. A row of LBL in the x-direction is switched tocorresponding global bit lines GBLs 330 by a set of pillar switches 340at their base. As will be described later, the set of pillar switches ispreferably implemented with a NAND selection using two select gates SGs341-1, 341-2.

For ease of illustration, FIG. 14 shows each word line segment 312 in amemory layer able to select 4 local bit lines. In practice, each wordline segment 312 can select other number of local bit lines in eachmemory layer. For example, if there are 8 memory layers, then, each wordline has 8 segments. If each segment can select 16 bit lines in eachmemory layer, then each word line can select 16×8=128 local bit lines inparallel across all 8 memory layers. The top segment is also connectedto a word line driver 350 formed by a source 352 and drain 354controlled by a WL select gate 351.

Adjacent Staircase Word Lines Offset in the X-Direction by the Pitch ofthe Local Bit Line

FIG. 15 illustrates a cross-section view of the 3D array along they-direction according to an embodiment in which the word line 310 stepto the next memory layer is made in between the bit lines. In thisexample, each word line segment 312 selects 8 local bit lines in eachstep or memory layer. There are 4 memory layers. Each step rises to thenext layer in between a pair of adjacent local bit lines 320. Adjacentstaircase word lines on adjacent layers are staggered so that theirrisers 314 have an offset 315 along the x-direction given by the pitchof the local bit lines. The R/W element cross-section, defined by thebit line and the word line, is constant.

Adjacent Staircase Word Lines Offset in the X-Direction by the Half thePitch of the Local Bit Line

FIG. 16 illustrates a cross-section view of the 3D array along they-direction according to an embodiment in which the various staggeredword line steps are stacked as close as possible. In this example, eachword line segment 312 selects 8 local bit lines in each step or memorylayer. There are 4 memory layers. Each step rises to the next layer inbetween a pair of adjacent local bit lines 320. Two adjacent staircaseword lines on adjacent layers are staggered so that their risers 314have an offset 315 given by half the pitch of the local bit lines. TheR/W element cross section differs. However, this configuration yieldsbetter array efficiency and has shorter word lines.

The advantage of the staircase word line architecture is that word linesfrom different memory layers can be accessed easily as each eventuallycan be accessed and selected from either the top or bottom of the 3Dmemory array. In this way, interconnect and decoding are much simplifiedand there is no need to have multiple word lines connected in parallelto share limited resources. This will avoid the individual word linedrivers having to drive a large load in the form of a large number ofword lines in parallel and the ICC can be reduced. Within a given ICCbudget, the performance is improved. Drivers implemented by devices withweaker drive power than CMOS devices may be used. Also, by avoidingmultiple word lines connected in parallel, disturb is reduced.

According to a first implementation of forming a slab of multi-planememory with staircase word lines, a word line layer and an oxide layerare alternately formed on top of each other. After a word layer isformed, trenches are cut in the word layer with a first mask to createword line segments having first and second ends. After an oxide layer isformed, trenches are cut in the oxide layer with a second mask to exposethe second end of each word line segment for connection to a first endof each word line segment in the next plane to create the staircasestructure. With each memory plane constituting from a word line layerand an oxide layer, this method requires two masking to form each memoryplane.

According to a first embodiment, the staircase word line is formed suchthat each segment in a plane crosses more than one vertical bit line.Thus, the formation of the alternate word lines and bit lines isaccomplished by offsetting a same mask each time by a width of thetrench.

FIG. 17 illustrates from top to bottom a series of process steps tofabricate a 3D array with staircase word lines. In this example, eachmemory layer is formed by two masking applications.

(1) A word line layer is deposited on a base surface. For example a 3 nmlayer of word line material is deposited by Atomic Layer Deposition(“ALD’). A masking layer with a first mask is laid over the word linelayer to enable trenches to be etched in the word line layer.

(2) Trenches are etched in the word line layer through the openings ofthe first mask to the base surface. An anisotropic word line etch isperformed using Reactive Ion Etch (“RIE”).

(3) An oxide layer is deposited on top of the word line layer. Forexample a 10 nm to 20 nm oxide is deposited by ALD. This is followed bya second mask process. The second mask is identical to the first maskexcept for an offset by the width of a trench to enable trenches to beetched in the oxide layer. The current trenches are aligned adjacent tothe previous trenches.

(4) Trenches are etched in the oxide layer through the openings of thesecond mask. An anisotropic oxide etch is performed using RIE.

(5) A second word line layer is formed on top of the oxide layer andmaking connection with the lower word line layer through the trenches inthe oxide layer. This is followed by the first mask being laid over thesecond word line layer but offset from the last mask by the width of atrench

(6) Trenches are etched in the second word line layer through theopenings of the first mask. An anisotropic word line etch is performedusing RIE. And so the process repeats itself as in 3) for the nextlayer.

Once the multi-layer slab is formed with the staircase word lines, theword lines layers can be isolated in the y-direction by cutting trenchesin the slab and forming vertical local bit lines in the trenches. Anexample of isolation and forming of the vertical local bit lines in a 3Dmemory slab is described in United State Patent Publication No.2012/0147650 A1, the entire disclosure of which is incorporated hereinby reference.

3D Array Architecture with Word Line Drivers on Top

According to yet another aspect of the invention, the word line driveris implemented as a word line driver layer on the top end of the 3Darray. This is accomplished by forming a TFT device in contact with atop segment of a staircase word line.

This is distinct from conventional implementation where the word linedriver is formed as CMOS devices on the substrate layer and contact ismade with a word line among the multiple memory layers by means ofvertical interconnects such as zias.

FIG. 18 illustrates a word line driver formed as a vertical structure ontop of the 3D array of memory layers. The word line driver 350 ispreferably implemented by a TFT transistor similar to the pillar selectdevice between the local bit line and the global bit line. The TFT (ThinFilm Transistor) device is a transistor form with its NPN junction asthree thin layer on top of each other so that it is oriented in thez-direction. The word line driver 350 can then switch between an exposedword line segment and a word line power source (not shown). The wordline driver can have a width as wide as the segment of a word line. FIG.18 shows two adjacent word line drivers 350-Even and 350-Odd,respectively switching two adjacent segments 312-Even and 312-Odd fromtwo adjacent word lines across the y-direction. It will be seen that theeven WL access line 355-Even along the y-direction accesses the evenbanks of word lines along the y-direction. Similarly, the odd WL accessline 355-Odd along the y-direction accesses the odd banks of word linesalong the y-direction. Each of these access lines only access alternateword line segment because these segments are not isolated by an oxidelayer 404.

The staircase word line architecture enables each word line to be accessfrom either top or bottom of the 3D memory array. In one embodiment,since the CMOS layer at the bottom is already crowded with metal linesand other active devices such as sense amplifiers and op amps, it isadvantageous to locate the word line drivers to the top of the 3D memoryarray. Even though TFT transistors are not as powerful as CMOS devices,it is possible to use them to drive the staircase word lines because theindividual word lines are easier to drive they are not extended and thedriver can be as wide as a segment of a word line.

Efficient 3D Array Architecture with Staircase Word Lines

The embodiments of 3D arrays with staircase word lines shown in FIG. 15and FIG. 16 each has L memory layers with each word line traversing thelayers in the form of a staircase. At each layer, a step of thestaircase crosses a segment of R local bit lines. Then the word linerises via a riser to the next layer to cross another segment therein.Thus, the array, as seen in the x-z plane, comprises a bank of local bitlines. The bit lines are oriented in the z-axis direction across allmemory layers and the bank is extended in the x-axis direction. Eachflight of staircase word line traverses the memory layers in the bankfrom a bottom edge to a top edge. In the x-z plane, the bank issuperimposed with multiple flights of staircase word line closelystacked in the x-axis direction, so that each memory layer is accessibleby a segment from a different flight of staircase word line.

Since the segments in each memory layer are all aligned along the samehorizontal baseline, they cannot be so tightly stacked in the x-axisdirection so as to prevent shorting among them. The embodiment shown inFIG. 15 has an offset of the pitch of a bit line between two segments.The embodiment shown in FIG. 16 has an offset of half the pitch of a bitline between two segments.

In general, if there are L layers, ideally each local bit line that runsacross all L layers should have an independent word line crossing ateach layer. However, it can be seen that in both the embodiment of FIG.15 and the embodiment of FIG. 16, not all the bit lines are crossed by aword line at every layer. These result from the finite offsets in theseembodiment and lead to inefficient utilization of space and resources.For example in FIG. 15, at the top layer, there is one bit line notcrossed by a word line for every R+1 bit lines. In this case, where R=8,it can be seen that for every 9 local bit lines, there is an idle one onthe top memory layer. Similarly, the same is true for the bottom memorylayer. For a total of 4 layers, and with a waste of 1 in 9 per top orbottom layer, this amounts to a loss in density of 2/(9×2), or a totalof 11%. If the number of layers is increased the loss in density isreduced. However, this will require more layers and also longer wordlines, which could lead to drawing excessive currents.

An efficient 3D array architecture with staircase word lines isimplemented with no offset between segments along each memory layer.Essentially this is accomplished by raising an end portion of eachsegment away from the horizontal baseline. In this way, there will beroom along the horizontal baseline at the end of the segment for thenext segment to be placed there.

FIG. 19A is a schematic illustration of a cross-section view of theefficient 3D array projected on the x-z plane. An example in thisembodiment has the number of memory layers to be L=4 and the number oflocal bit lines LBL crossed by a segment of a word line in each memorylayer to be R=4. At each memory layer, instead of having each word lineWL segment crossing horizontally the R=4 local bit lines, it is made toramp up as it crosses the 4 local bit lines so that the crossing withthe next bit line is higher in the z-axis direction compared to that ofthe current bit line. In this embodiment, the ramping up is uniformacross the bit lines. In the example shown where R=4, the ramp up of thesegment consists of stepping up after crossing each of the four localbit lines in the segment. In this way, for each memory layer, towardsthe end of each segment, the bulk of the segment will be raised awayfrom the horizontal baseline. This allows room for the next segment tofollow immediately along the horizontal baseline.

In this example, essentially each word line has 4 ramping segments, onefor each memory layer, and each segment crosses 4 local bit lines. Thus,each word line crosses 16 local bit lines across the 4 memory layers. Itis possible to have different word line lengths. For example, a shortestramping word line segment can be crossing just 2 local bit lines permemory layer (i.e., R=2). In that case, the pitch of the word linedrivers will be 2 local bit lines. For a memory with 4 layers (i.e.,L=4), each word line will cross R×L=2×4=8 local bit lines.

FIG. 19B illustrates the device structure of the efficient 3D arrayshown schematically in FIG. 19A. In one embodiment, the local bit linesand word lines are formed from doped polysilicon.

FIG. 20 is a schematic illustration of a cross-section view of theefficient 3D array projected on the x-z plane according to anotherembodiment. In this embodiment, the word line segment in a layer crossesthe local bit lines horizontally similar to that shown in FIG. 15 andFIG. 16 but rises up to cross the last one or two bit lines near the endof the segment. This allows room for the next segment to followimmediately along the horizontal baseline without skipping a bit line.

The efficient 3D array architecture avoids the wastage associated withthe embodiments shown in FIG. 15 and FIG. 16. As can be seen from FIG.19, the bank of local bit lines are essentially traversed by uniformflights of staircase word line, except for the ones (shown in grey-outshade) near the left and right edges of the bank. These edge exceptionscan be ignored or not formed at all. Even though a small number of localbit lines are depicted in the bank shown in FIG. 19 for ease ofillustration, in practice there are many more local bit lines. Given thevast majority of regular bit lines in the core of the bank, the wastagedue to the edge is diminishing.

FIG. 21 is an isometric view of a portion of an efficient 3D arraysimilar to that shown in FIG. 19A. The gross structure is a 3D array ofmemory cells (R/W material) at crossings between a 2D array of local bitlines LBLs 320 in the z-direction and segments 312 of word lines WLs 310in each memory layer in the x-y plane. For ease of illustration, FIG. 21shows one row of LBLs 320 crossed by flights of staircase word linesalong the x-direction. Each staircase word line has one step per bitline. The WL segment in this case is of staircase form and is able toselect 6 local bit lines. In this embodiment, the word line driver 450is located at the bottom of the 3D array on the substrate side. Thisallows an alternative architecture of the global bit lines GBL 330 beingpositioned on the top of the 3D array with corresponding switches 440 toaccess the local bit lines LBL 320.

A first embodiment of a first implementation of forming a slab ofmulti-plane memory with staircase word lines has been described inconnection with FIG. 17(1) to FIG. 17(6)

According to a second embodiment, the staircase word line is formed suchthat each segment in a plane crosses one vertical bit line. Thus, theformation of the alternate word lines and bit lines is accomplished byoffsetting a mask that creates trenches that are separated by a width ofa trench and by offsetting the mask each time by half a width of thetrench.

FIG. 22A-FIG. 22H illustrate a series of process steps to fabricate theefficient 3D array shown in FIG. 19.

In FIG. 22A, a masking layer 402 is laid over the word line layer 410 toenable trenches to be etched in the word line layer.

In FIG. 22B, trenches are etched in the word line layer.

In FIG. 22C, an oxide layer 404 is deposited on top of the word linelayer, followed by the same masking layer but offset by half a trenchlength to the left to enable trenches to be etched in the oxide layer.The current trenches are offset to the previous trenches by half atrench length each.

In FIG. 22D, trenches are etched in the oxide layer.

In FIG. 22E, a second word line layer is formed on top of the oxidelayer and making connection with the lower word line layer through thetrenches in the oxide layer. This is followed by the same masking layerbut offset by yet another half a trench length to the left over thesecond word line layer.

In FIG. 22F, Trenches are etched in the second word line layer.

In FIG. 22G, the process repeats itself as in that shown in FIG. 22C forthe next layer of oxide and masking layer to build up the staircasestructure of the word line.

In FIG. 22H, the process repeats itself as in that shown in FIG. 22Dwhere trenches are etched in the oxide layer in order to build upprogressively the staircase structure of the word line.

FIG. 23 illustrates the biasing condition for setting or resetting a R/Welement. For simplicity of illustration, the biasing voltages are 0V (nobias), 1V (half bias) and 2V (full bias). An R/W element is selected forsetting or resetting when it is exposed to the full bias voltage of 2V.This is arranged with the selected local bit line LBL set to full biasof 2V and the selected word line WL set to no bias of 0V in order todevelop maximum potential difference across the selected R/W element. Toprevent the other R/W elements from changing state, all other unselectedWLs and LBLs are set to half bias of 1V so that each will see a maximumof 1V potential difference. It will be seen that the unselected bitlines and word lines are still drawing current at half bias. Asexplained above, a short word line is preferable as it will allow ICCcurrent consumption to be under control.

High Capacity Vertical Switches for Local Bit Lines

According to a general context of the invention, a nonvolatile memory isprovided with a 3D array of read/write (R/W) memory elements accessibleby an x-y-z framework of an array of local bit lines or bit line pillarsin the z-direction and word lines in multiple layers in the x-y planeperpendicular to the z-direction. An x-array of global bit lines in they-direction is switchably coupled to individual ones of the local bitline pillars along the y-direction. This is accomplished by a verticalswitch between each of the individual local bit line pillars and aglobal bit line. Each vertical switch is a pillar select device in theform of a thin film transistor that is formed as a vertical structure,switching between a local bit line pillar and a global bit line. Thethin film transistor, in spite of its structural shortcoming, isimplemented to switch a maximum of current carried by the local bit lineby a strongly coupled select gate which must be fitted within the spacearound the local bit line.

In one embodiment, maximum thickness of the select gate is implementedwith the select gate exclusively occupying the space along thex-direction from both sides of the local bit line. In order to be ableto switch all bit lines in a row, the switches for odd and even bitlines of the row are staggered and offset in the z-direction so that theselect gates of even and odd local bit lines are not coincident alongthe x-direction.

As shown earlier (e.g., in FIG. 21), the each row of local bit lines LBL320 along the x-direction are selectively switched to a set of globalbit lines by a corresponding set of (pillar or LBL to GBL) switches 440.One end of each local bit line along the z-axis direction is switchablyconnected to a global bit line GBL 330 along the y-axis direction.

FIG. 24A is a perspective view illustrating an architecture for highcapacity local bit line switches. Essentially, the switch is a TFTtransistor formed vertically adjacent to a local bit line in the 3Darray built on top of the CMOS substrate. An issue is that TFTtransistors are relatively not as powerful as CMOS transistors andtherefore their current capacity must be maximized by maximizing theirsize and surface area. Since there is a TFT transistor for each localbit line, it is preferably formed in-line at one end of the local bitline. Thus the LBLs can be switched either from below or from topdepending on the location of the GBLs. The TFT transistor 342 has a TFTtransistor junction (also known as a TFT transistor body region) 343that is formed by a P-doped polysilicon layer between two N-dopedpolysilicon layers. A thin gate oxide 404 separates the TFT transistorjunction 343 from a select gate such as select gate 341-1 or select gate341-2. In this way a NPN transistor is formed in line with the local bitline or bit line pillar. Since the gate oxide 404 and the gate have tobe formed in a space between two local bit lines, the gates are limitedin size if each gate switches one bit line and not the adjacent bitline.

In the preferred embodiment, the TFT transistors of adjacent rows of bitlines are not aligned horizontally, rather they are staggered as shownin FIG. 24A with an offset in the z-direction. In this way, the spaceadjacent each TFT transistor junction 343 can be used exclusively toform the gate for that TFT, thereby maximizing the size of the gate.Referring to FIG. 1 and FIG. 24A at the same time, it can be seen FIG.24A shows the 2D array of LBLs, where LBLij is in the ith column and jthrow. Thus, for example in a first (or ODD) row of local bit lines, suchas LBL11, LBL21, LBL31, . . . , the TFT transistor 342-10 are all at thesame vertical position. In the second (or EVEN) row of local bit lines,such as LBL12, LBL22, LBL32, . . . , the TFT transistors 342-2E are alloffset from the TFT transistors 342-10 along the z-direction. Thusselecting the ODD row will not select an adjacent EVEN row and viceversa.

In operation, a select signal is applied to an even select lineconnecting all the even TFT transistors to selectively connect an evenrow of local bit lines to corresponding global bit lines. Similarly, aselect signal is applied to an odd select line connecting all the oddTFT transistors to selectively connect an odd row of local bit lines tocorresponding global bit lines.

In yet another embodiment, the efficacy of the TFT transistor is furtherenhanced when the gate is formed by wrapping around the TFT transistorjunction, thereby increasing the surface area of the gate to the TFTtransistor junction.

FIG. 25 illustrates a cross sectional view of the switch shown in FIG.24A along the line z-z. The select gate 342-2 (select gate 2) wrapsaround the TFT 343-2 and the channel width of the TFT transistorjunction is effective quadrupled, with conduction on all four sides.

Even and Odd TFT Transistors at Opposite Surfaces of the Memory Layers

FIG. 24B illustrates another embodiment of the high capacity local bitline switches. It is similar to that shown in FIG. 24A except the ODDand EVEN set of TFT transistors are located on opposite sides of thememory layer. The even TFT transistor junctions such as 343-2, 343-4, .. . are used to switch even rows of local bit lines to a first set ofglobal bit lines on one side 302-2 of the memory layer and the odd TFTtransistor junctions, such as 343-1 are used to switch odd rows of localbit lines to a second set of global bit lines at an opposite side 302-1of the memory layer. Any of the select gates in FIG. 24B wrap around theassociated TFT; for example the select gate 342-2 (select gate 2E) asshown in FIG. 25 wraps around the TFT 343-2 and the channel width of theTFT transistor junction is effectively quadrupled, with conduction onall four sides.

FIG. 26 illustrates the vertical select device in the overall scheme ofan exemplary 3D memory device in a cross-sectional view from they-direction along the global bit lines and perpendicular to the wordlines. Essentially, the 3D memory device comprises five gross layers: aCMOS and metal layer; a vertical switch layer 1; a memory layerdelineated by surfaces 302-1 and 302-2; a vertical switch layer 2 and atop metal layer. The 3D memory elements are fabricated in a memory layeron top of the CMOS and metal layer. In the CMOS and metal layer, theCMOS provides a substrate for forming CMOS devices and for supportingthe other gross layers on top of it. On top of the CMOS there may beseveral metal layers, such as metal layer-0, metal layer-1 and metallayer-2. The vertical select layer 1 and layer 2 contain similarvertical select switches in the form of thin-film transistors (TFTs)which provide selective access to the word lines WLs and local bit linesLBLs in the memory layer.

In one 3D architecture shown in FIG. 8, the global bit lines GBLs are atthe bottom of the memory layer and therefore are formed as one of thesemetal layers, such as metal layer-1 or metal layer-2. The verticalswitch layer 1 then contains the LBL to GBL switches connecting the GBLsto the vertical local bit lines in the memory layer. Access to the wordline are via the top metal layer from the top side the memory layer andtherefore the word line drivers are implemented in the vertical switchlayer 2 connecting each word line to a metal pad at top metal layer.

In the embodiment illustrated in FIG. 24B with even and odd TFTs atopposite surfaces of the memory layer, the even GBLs (330-2, 330-4, . .. ) are at a first surface 302-2 of the memory layer and the odd GBLs(330-1, 330-3, . . . ) are at a second surface 302-1 opposite the firstsurface of the memory layer. Thus there is double the space at each endto form each TFT transistor switch. The TFT transistors and the globalbit lines can be made bigger to conduct higher currents. This embodimentis applicable for 3D memory that does not use one of the vertical switchlayers (e.g., that shown in FIG. 8) for switching word lines so thatboth vertical switch layer 1 and vertical switch layer 2 can be devotedseparately to even and odd switches for switching local bit lines.

Method for Forming a Surround Gate of Vertical Switch in a 3D Memory

According to a general context of the invention, a nonvolatile memory isprovided with a 3D array of read/write (R/W) memory elements accessibleby an x-y-z framework of an array of local bit lines or bit line pillarsin the z-direction and word lines in multiple layers in the x-y planeperpendicular to the z-direction. An x-array of global bit lines in they-direction is switchably coupled to individual ones of the local bitline pillars along the y-direction. This is accomplished by a selecttransistor between each of the individual local bit line pillars and aglobal bit line. Each select transistor is a pillar select device thatis formed as a vertical structure, switching between a local bit linepillar and a global bit line.

The vertical switches such as (LBL to GBL switches) as well as the wordline drivers shown in FIG. 21 are preferably implemented by a bank ofvertically aligned (z-axis) TFTs, each controlled by a surround gate.For example, as shown in FIG. 21, the surround gates for the LBL to GBLswitches form a LBL row select line along the x-axis which selects a rowof LBLs.

FIG. 26 illustrates the vertical select device in the overall scheme ofan exemplary 3D memory device in a cross-sectional view from they-direction along the global bit lines and perpendicular to the wordlines. Essentially, the 3D memory device comprises five gross layers: aCMOS and metal layer; a vertical switch layer 1; a memory layer; avertical switch layer 2 and a top metal layer. The 3D memory elementsare fabricated in a memory layer on top of the CMOS and metal layer. Inthe CMOS and metal layer, the CMOS provides a substrate for forming CMOSdevices and for supporting the other gross layers on top of it. On topof the CMOS there may be several metal layers, such as metal layer-0,metal layer-1 and metal layer-2. The vertical select layer 1 and layer 2contain similar vertical select switches in the form of thin-filmtransistors (TFTs) which provide selective access to the word lines WLsand local bit lines LBLs in the memory layer.

In one 3D architecture shown in FIG. 8, the global bit lines GBLs are atthe bottom of the memory layer and therefore are formed as one of thesemetal layers, such as metal layer-1 or metal layer-2. The verticalswitch layer 1 then contains the LBL to GBL switches connecting the GBLsto the vertical local bit lines in the memory layer. Access to the wordline are via the top metal layer from the top side the memory layer andtherefore the word line drivers are implemented in the vertical switchlayer 2 connecting each word line to a metal pad at top metal layer.

In another 3D architecture shown in FIG. 21, the top and bottom accessto the word lines WLs and global bit lines GBLs are reversed. Inparticular, the GBLs are formed as a top metal layer above of the memorylayer.

According to another aspect of the invention, a 3D memory devicecomprises a vertical switching layer which serves to switch a set oflocal bit lines to a corresponding set of global bit lines, the verticalswitching layer being a 2D array of TFT channels of vertical thin-filmtransistors (TFTs) aligned to connect to the array of local bit lines,each TFT switching a local bit line to a corresponding global bit lineand each TFT having a surround gate. In particular, the TFTs in thearray have a separation of lengths Lx and Ly along the x- and y-axisrespectively such that a gate material layer forms a surround gatearound each TFT in an x-y plane and has a thickness that merges to forma row select line along the x-axis while maintaining a separation oflength Ls between individual row select lines.

According to another aspect of the invention, in a 3D memory device withstructures arranged in a three-dimensional pattern defined byrectangular coordinates having x, y and z-directions and with aplurality of parallel x-y planes stacked in the vertical z-directionover a semiconductor substrate, and including a memory layer, a methodof forming a vertical switching layer which provides access to thememory layer comprises forming a 2-D array of TFT channels of verticalthin-film transistors (TFTs) to provide switching access to structuresin the memory layer, forming a gate oxide layer wrapping around each TFTchannel in the x-y plane, and forming a gate material layer over of thegate oxide layer, wherein the TFT channels in the 2-D array have aseparation of lengths Lx and Ly along the x- and y-axis respectively andsuch that said gate material layer has a thickness that merges to form arow select line along the x-axis while maintaining a separation oflength Ls between individual row select lines.

Generally, compared to CMOS transistors, thin-film transistors (TFTs) donot handle as much current. Having a surround gate effectively increasesthe channel area of the TFT and provides improved switching or drivingcapacity. The surrounding gate can deliver 3 times the drive currentcompared to a conventional single-side gate.

FIG. 27 is a schematic view in the x-y plane of a cross-section of thevertical switches in the select layer 2 for the 3D architecture shown inFIG. 21. As described earlier, each TFT channel is controlled by asurround gate to provide maximum switching or driving capacity. In thiscase, the surround gates for a row of TFT channels along the x-axis aremerged together to form a row select line while individual row selectlines are isolated from each other across the y-axis. Each TFT switchesbetween a vertical bit line LBL and a global bit line GBL. The rowselect line controls the switching of a row of vertical bit lines alongthe x-axis.

In one example, Lx=24 nm and Ly=48 nm instead of a conventional exampleof 24 nm×24 nm. As mentioned earlier, the surrounding gate can deliver 3times the drive current compared to a conventional single-side gate. Therequired TFT's Ids is reduced from 256 uA/um to 85 uA/um.

FIG. 28 to FIG. 35 illustrate the processes of forming of the verticalswitch layer 2. Essentially, a slab of channel material is formed on topof the memory layer. Then the slab is etched to leave a 2D array ofindividual channel pillars. The separations between channel pillars havea predetermined aspect ratio given by Lx along the x-axis and Ly alongthe y-axis and where Ly−Lx=Ls. Then gate oxide layer and gate materiallayer are deposited to form the individual TFTs. In particular, the gatematerial layer is deposited to a thickness that the gate layers ofneighboring channels just merged together. This will form a gate selectline for each row of TFTs along the x-axis while leaving a separation ofLs between adjacent gate select lines. As can be seen from FIG. 27, Lsis the thickness of the oxide isolating two adjacent gate select linesand therefore must be of sufficient thickness for the oxide to withstandan operating voltage without electrical breakdown.

FIG. 28 illustrates the processes of depositing a layer of N+ poly ontop of the memory layer, followed by depositing a layer of P− poly andthen a layer of N+ poly. This will form a NPN slab suitable forfashioning individual channel pillars for the TFTs.

FIG. 29A is a perspective view of the vertical switch layer 2 on top ofthe memory layer and illustrates the processes of forming the individualchannel pillars from the NPN slab. Each channel pillar is aligned andformed to switch a local bit line LBL in the memory layer below. This isaccomplished by photo patterning hard masking and then RIE (Reactive IonEtch) etching trenches to the top of the memory layer to isolate theslab into individual channel pillars.

FIG. 29B illustrates a top plan view of FIG. 29A after the individualchannel pillars have been formed. As described earlier, the separationbetween two adjacent channel pillars along the x-axis is Lx and theseparation between two adjacent channel pillars along the y-axis is Ly,where Ly=Lx+Ls. The bottom of each channel pillar is connected to alocal bit line in the memory layer. The top of each channel pillar willbe connected a global bit line GBL to be formed on the top metal layer.

FIG. 30A is a cross-sectional view along the x-axis illustratingdepositing a gate oxide layer on top of the channel pillars. Forexample, a layer of about 5 nm is formed by Atomic Layer Deposition(“ALD’).

FIG. 30B is a cross-sectional view along the y-axis of FIG. 30A.

FIG. 31A is a cross-sectional view along the x-axis illustratingdepositing a gate material layer on top of the gate oxide layer. Thedeposition is accomplished by Atomic Layer Deposition (“ALD’) or LowPressure Chemical Vapor Deposition (“LPCVD”). The deposited gatematerial layer wraps around each channel pillar to form a surround gate.The thickness of the layer is controlled so that the layers fromneighboring channels merge into a single gate select line along thex-axis but individual gate select lines remain isolated from each otherwith a spacing of Ls (see also FIG. 27). For example, the gate layer is7 nm of TiN and together with the gate oxide layer of 5 nm amount to 12nm. If Lx=24 nm, adjacent gates along the x-direction will merge.

FIG. 31B is a cross-sectional view along the y-axis of FIG. 31A showingthat the spacing between adjacent pair of insulated channel pillar arefilled with the gate material. If Ly=48 nm, then Ls=24 nm.

FIG. 32A is a cross-sectional view along the x-axis illustrating furtheretch back of the gate material layer. A mixture of anisotropic andisotropic etches of high selectivity serves to remove the gate materiallayer from the top of each channel pillar and at the floor betweenchannel pillars along the y-axis and recess the wrapped-around side wallof the layer from the top of each channel pillar. After selectiveremoval of the gate material, the exposed N+ layer at the top of eachchannel pillar is planarized.

FIG. 32B is a cross-sectional view along the y-axis of FIG. 32A. It willbe seen that the gate material are now wrapping around each channelpillar and forming a continuous select gate line along the x-axis whileeach select gate line for each row of channel pillars along the x-axisare isolated from each other by a separation of Ls (see also FIG. 32A).

FIG. 33A is a cross-sectional view along the x-axis illustrating theprocess of depositing oxide to fill in any pits and gaps to complete thevertical switch layer 2. The oxide fill is followed by planarization.

FIG. 33B is a cross-sectional view along the y-axis of FIG. 33A of thecompleted vertical switch layer 2 having an array of TFTs controlled byselect gate lines along the x-axis.

FIG. 34A is a cross-sectional view along the x-axis illustrating theprocess of forming global bit lines GBLs in the top metal layer. EachGBL line is connected to the top of channel pillars along a row in they-axis.

FIG. 34B is a cross-sectional view along the y-axis of FIG. 34A.

FIG. 35 is a cross-sectional view along the x-axis illustrating theprocess of filling in the gaps between metal lines. This is thenfollowed by planarization to complete the vertical switch layer.

CONCLUSION

Although the various aspects of the present invention have beendescribed with respect to exemplary embodiments thereof, it will beunderstood that the present invention is entitled to protection withinthe full scope of the appended claims.

It is claimed:
 1. A 3D memory having memory elements arranged in athree-dimensional pattern defined by rectangular coordinates having x, yand z-directions and with a plurality of parallel planes stacked in thez-direction, said memory having a multi-layer structure on top of asubstrate, the multi-layer structure including a multi-plane memorylayer, said 3D memory further comprising: a 2-D array in an x-y plane ofconductive pillars as bit line pillars elongated in the z-directionthrough the plurality of planes, the 2-D array of bit line pillars beingspaced apart in the x-direction and the y-direction by a spacing Lx anda spacing Ly respectively and a difference between the spacing Ly andthe spacing Lx given by a spacing Ls; a 2D array of isolated TFTchannels in the x-y plane, each TFT channel being in-line with andhaving a first end connected to one end of one of the bit line pillarsalong the z-direction; a layer of gate material surrounding each TFTchannel but isolated from the TFT channel by an intermediate oxidelayer, said layer of gate material having a thickness that fills a spacebetween adjacent TFT channels in the x-direction to form a select gateline along the y-direction, thereby leaving a select gate with at leasthalf of said thickness surrounding each TFT channel while leaving aspace of Ls between adjacent TFT channels along the y-direction; andindividual metal lines along the y-direction, each metal line in contactwith a second end of a TFT channel among a column of bit lines in they-direction.
 2. The 3D memory as in claim 1, wherein: each TFT channelfurther comprises: a first layer of N+ doped polysilicon; a second layerof P− doped polysilicon; and a third layer of N+ doped polysilicon. 3.The 3D memory as in claim 1, wherein: the conductive pillars are formedfrom polysilicon.
 4. The 3D memory as in claim 1, wherein: an isolatingoxide layer is between two adjacent select gate lines; and the isolatingoxide layer has a thickness given by the spacing Ls.
 5. The 3D memory asin claim 1, wherein: the spacing Ls gives the isolating oxide layer witha thickness that is able to withstand a operating voltage withoutelectrical breakdown.
 6. The 3D memory as in claim 1, wherein: whereinthe memory elements are non-volatile reprogrammable memory elements. 7.The 3D memory as in claim 6, wherein: the non-volatile reprogrammablememory elements each has a resistance that reversibly shift inresistance in response to a voltage applied to or current passed throughthe material.
 8. A method of forming a vertical switch layer in a 3Dmemory having memory elements arranged in a three-dimensional patterndefined by rectangular coordinates having x, y and z-directions and witha plurality of parallel planes stacked in the z-direction, said memoryhaving a multi-layer structure on top of a substrate, the multi-layerstructure including a multi-plane memory layer, said method comprising:providing in the multi-plane memory layer a 2-D array in an x-y plane ofconductive pillars as bit line pillars elongated in the z-directionthrough the plurality of planes, the 2-D array of bit line pillars beingspaced apart in the x-direction and the y-direction by a spacing Lx anda spacing Ly respectively and a difference between Ly and Lx given by aspacing Ls; forming a slab of a vertical switch layer on top of themulti-plane memory layer by forming a 2D array of isolated TFT channelsin the x-y plane of the slab, each TFT channel being in-line with andhaving a first end connected to one end of one of the bit line pillarsalong the z-direction; depositing a layer of gate oxide on the slab;forming a select gate surrounding each TFT channel by depositing a layerof gate material on top of the layer of gate oxide, said layer of gatematerial having a thickness that fills a space between adjacent TFTchannels in the x-direction to form a select gate line along they-direction, thereby leaving a select gate with at least half of saidthickness surrounding each TFT channel while leaving a space of Lsbetween adjacent TFT channels along the y-direction; exposing a top endof each TFT channel by selectively etching back the gate material andthe oxide deposited on the top end of each TFT channel; filling any pitsin the vertical switch layer by depositing oxide followed byplanarization; and forming individual metal lines along the y-direction,each metal line in contact with a second end of a TFT channel among of acolumn of bit lines in the y-direction.
 9. The method as in claim 8,wherein said forming a 2D array of isolated TFT channels furthercomprises: depositing three layers of doped polysilicon to form achannel structure for a thin film transistor (“TFT”) aligned in thez-direction; masking and etching portions of the three layers of dopedpolysilicon to form the 2D array of isolated TFT channels in the x-yplane, each TFT channel being in-line with and connected to one end ofone of the bit line pillars along the z-direction.
 10. The method as inclaim 7, wherein said three layers of doped polysilicon are a firstlayer of N+ doped polysilicon followed by a second layer of P− dopedpolysilicon and followed by a third layer of N+ doped polysilicon. 11.The method as in claim 8, wherein said forming individual metal linesfurther comprises: depositing a metal layer over the vertical switchlayer; masking and etching portions of the metal layer to isolate theindividual metal lines along the y-direction, each metal line in contactwith the TFT channels of a column of bit lines in the y-direction; andfilling any gaps in the vertical switch layer by depositing oxidefollowed by planarization.
 12. The method as in claim 8, wherein: theconductive pillars are formed from polysilicon.
 13. The method as inclaim 8, wherein: said filling any pits in the vertical switch layer bydepositing oxide followed by planarization create an isolating oxidelayer between two adjacent select gate lines; and the isolating oxidelayer has a thickness given by the spacing Ls.
 14. The method as inclaim 13, wherein: the spacing Ls gives the isolating oxide layer with athickness that is able to withstand a operating voltage withoutelectrical breakdown.
 15. The method as in claim 8, wherein the memoryelements are non-volatile reprogrammable memory elements.
 16. The methodas in claim 15, wherein the non-volatile reprogrammable memory elementseach has a resistance that reversibly shift in resistance in response toa voltage applied to or current passed through the material.